[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

I think we will want decoding tests as well, at least one for instruction.

One example follows:

  # RUN: llvm-mc --disassemble --triple riscv64 -mattr +v < %s | \
  # RUN:         FileCheck %s
  
  # CHECK: vmerge.vvm v1, v3, v2, v0
  [0xd7,0x00,0x31,0x5c]


Repository:
  rL LLVM

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  https://reviews.llvm.org/D69987/new/

https://reviews.llvm.org/D69987