[PATCH] D70090: [ARM] -mfpu=*-sp-d16 should imply that D registers are available

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham requested changes to this revision.
simon_tatham added a comment.
This revision now requires changes to proceed.

As I understand it, this has the effect of making the `VMOVD` and `VMOVDcc` instructions (e.g. `vmov.f64 d0,d1`) legal on targets with single-precision only FP, such as Cortex-M4. But by my reading of the 7-M ARMARM, I don't believe that instruction actually //is// legal on Cortex-M4.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70090/new/

https://reviews.llvm.org/D70090