[PATCH] D70090: [ARM] -mfpu=*-sp-d16 should imply that D registers are available

[Mikhail Maltsev via Phabricator via llvm-commits]

miyuki created this revision.
miyuki added reviewers: t.p.northover, momchil.velikov, ostannard, simon_tatham.
Herald added subscribers: llvm-commits, dmgreen, hiraditya, kristof.beyls.
Herald added a project: LLVM.

When using e.g. the following arch/fpu:

  -march=armv8-m.main -mfpu=fpv5-sp-d16

the target feature `fpregs64` is not enabled, i.e. D registers are not
allowed in any instruction. Even though 64-bit FP operations are not
available with such FPU option, the 64-bit D registers must still be
accessible (d16 implies that there are 16 D registers). This should
be the case for any `*-sp-d16` FPU.

This change also adjusts one MVE test.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70090

Files:
  llvm/lib/Target/ARM/ARM.td
  llvm/test/MC/ARM/mve-fp-registers.s


Index: llvm/test/MC/ARM/mve-fp-registers.s
===================================================================
--- llvm/test/MC/ARM/mve-fp-registers.s
+++ llvm/test/MC/ARM/mve-fp-registers.s
@@ -27,7 +27,7 @@
 // the FP64 instructions are optional. They are also limited to 16 D registers,
 // but we don't test that here.
 // RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4d16sp 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32
-// RUN: FileCheck %s < %t --check-prefix=NOFP16 --check-prefix=NOFP64
+// RUN: FileCheck %s < %t --check-prefix=NOFP16
 // RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4,-d32 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
 // RUN: FileCheck %s < %t --check-prefix=NOFP16
 
Index: llvm/lib/Target/ARM/ARM.td
===================================================================
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -65,7 +65,7 @@
     description#" with only 16 d-registers and no double precision",
     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
       !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
-      otherimplies>;
+      otherimplies # [FeatureFPRegs64]>;
   def _SP: SubtargetFeature<
     name#"sp", query#"SP", "true",
     description#" with no double precision",


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70090.228710.patch
Type: text/x-patch
Size: 1362 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191111/e1069d10/attachment.bin>