[llvm] d384ad6 - [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 00:23:34 PST 2019
Author: joanlluch
Date: 2019-11-13T09:23:08+01:00
New Revision: d384ad6b636d4a8c55ef53d5316d008a05161b1f
URL: https://github.com/llvm/llvm-project/commit/d384ad6b636d4a8c55ef53d5316d008a05161b1f
DIFF: https://github.com/llvm/llvm-project/commit/d384ad6b636d4a8c55ef53d5316d008a05161b1f.diff
LOG: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4)
Summary:
Replaces
```
unsigned getShiftAmountThreshold(EVT VT)
```
by
```
bool shouldAvoidTransformToShift(EVT VT, unsigned amount)
```
thus giving more flexibility for targets to decide whether particular shift amounts must be considered expensive or not.
Updates the MSP430 target with a custom implementation.
This continues D69116, D69120, D69326 and updates them, so all of them must be committed before this.
Existing tests apply, a few more have been added.
Reviewers: asl, spatel
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70042
Added:
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/lib/Target/MSP430/MSP430ISelLowering.h
llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 517c72ccbf2d..d0706c2320ec 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2608,10 +2608,10 @@ class TargetLoweringBase {
// same blocks of its users.
virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
- // Return the shift amount threshold for profitable transforms into shifts.
- // Transforms creating shifts above the returned value will be avoided.
- virtual unsigned getShiftAmountThreshold(EVT VT) const {
- return VT.getScalarSizeInBits();
+ /// Return true if creating a shift of the type by the given
+ /// amount is not profitable.
+ virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const {
+ return false;
}
//===--------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 09858e0ac7e0..9e9be97c665a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9401,7 +9401,7 @@ static SDValue foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG,
SDLoc DL(N);
unsigned ShCt = VT.getSizeInBits() - 1;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (ShCt <= TLI.getShiftAmountThreshold(VT)) {
+ if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) {
SDValue NotX = DAG.getNOT(DL, X, VT);
SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT);
auto ShiftOpcode =
@@ -19958,7 +19958,7 @@ SDValue DAGCombiner::foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0,
auto *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) {
unsigned ShCt = XType.getSizeInBits() - N2C->getAPIntValue().logBase2() - 1;
- if (ShCt <= TLI.getShiftAmountThreshold(XType)) {
+ if (!TLI.shouldAvoidTransformToShift(XType, ShCt)) {
SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy);
SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt);
AddToWorklist(Shift.getNode());
@@ -19976,7 +19976,7 @@ SDValue DAGCombiner::foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0,
}
unsigned ShCt = XType.getSizeInBits() - 1;
- if (ShCt > TLI.getShiftAmountThreshold(XType))
+ if (TLI.shouldAvoidTransformToShift(XType, ShCt))
return SDValue();
SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy);
@@ -20097,7 +20097,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
// Shift the tested bit over the sign bit.
const APInt &AndMask = ConstAndRHS->getAPIntValue();
unsigned ShCt = AndMask.getBitWidth() - 1;
- if (ShCt <= TLI.getShiftAmountThreshold(VT)) {
+ if (!TLI.shouldAvoidTransformToShift(VT, ShCt)) {
SDValue ShlAmt =
DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS),
getShiftAmountTy(AndLHS.getValueType()));
@@ -20154,7 +20154,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
return Temp;
unsigned ShCt = N2C->getAPIntValue().logBase2();
- if (ShCt > TLI.getShiftAmountThreshold(VT))
+ if (TLI.shouldAvoidTransformToShift(VT, ShCt))
return SDValue();
// shl setcc result by log2 n2c
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 96894613b4a5..6bb55b9b0cbd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3626,7 +3626,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// Perform the xform if the AND RHS is a single bit.
unsigned ShCt = AndRHS->getAPIntValue().logBase2();
if (AndRHS->getAPIntValue().isPowerOf2() &&
- ShCt <= TLI.getShiftAmountThreshold(ShValTy)) {
+ !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
DAG.getConstant(ShCt, dl, ShiftTy)));
@@ -3636,7 +3636,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
// Perform the xform if C1 is a single bit.
unsigned ShCt = C1.logBase2();
if (C1.isPowerOf2() &&
- ShCt <= TLI.getShiftAmountThreshold(ShValTy)) {
+ !TLI.shouldAvoidTransformToShift(ShValTy, ShCt)) {
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
DAG.getConstant(ShCt, dl, ShiftTy)));
@@ -3655,7 +3655,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
const APInt &AndRHSC = AndRHS->getAPIntValue();
if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
unsigned ShiftBits = AndRHSC.countTrailingZeros();
- if (ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) {
+ if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
SDValue Shift =
DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0),
DAG.getConstant(ShiftBits, dl, ShiftTy));
@@ -3684,7 +3684,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
NewC.lshrInPlace(ShiftBits);
if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
isLegalICmpImmediate(NewC.getSExtValue()) &&
- ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) {
+ !TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0,
DAG.getConstant(ShiftBits, dl, ShiftTy));
SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy);
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index b6a658f30a8c..37e6ea24d088 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -358,9 +358,10 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
}
}
-// Set transforms into shift amounts above 2 as not profitable
-unsigned MSP430TargetLowering::getShiftAmountThreshold(EVT VT) const {
- return 2;
+// Define non profitable transforms into shifts
+bool MSP430TargetLowering::shouldAvoidTransformToShift(EVT VT,
+ unsigned Amount) const {
+ return !(Amount == 8 || Amount == 9 || Amount<=2);
}
// Implemented to verify test case assertions in
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.h b/llvm/lib/Target/MSP430/MSP430ISelLowering.h
index 64ddbbdf6c84..650f9a704062 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.h
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.h
@@ -125,7 +125,7 @@ namespace llvm {
bool isZExtFree(SDValue Val, EVT VT2) const override;
bool isLegalICmpImmediate(int64_t) const override;
- unsigned getShiftAmountThreshold(EVT VT) const override;
+ bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI,
diff --git a/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
index 68bbe811e63e..8166c4688f3d 100644
--- a/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
+++ b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
@@ -153,9 +153,8 @@ entry:
define i16 @testSimplifySetCC_0_sh8(i16 %x) {
; CHECK-LABEL: testSimplifySetCC_0_sh8:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: bit #256, r12
-; CHECK-NEXT: mov r2, r12
-; CHECK-NEXT: and #1, r12
+; CHECK-NEXT: and #256, r12
+; CHECK-NEXT: swpb r12
; CHECK-NEXT: ret
entry:
%and = and i16 %x, 256
@@ -169,9 +168,8 @@ entry:
define i16 @testSimplifySetCC_1_sh8(i16 %x) {
; CHECK-LABEL: testSimplifySetCC_1_sh8:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: bit #256, r12
-; CHECK-NEXT: mov r2, r12
-; CHECK-NEXT: and #1, r12
+; CHECK-NEXT: and #256, r12
+; CHECK-NEXT: swpb r12
; CHECK-NEXT: ret
entry:
%and = and i16 %x, 256
@@ -185,13 +183,8 @@ entry:
define i16 @testShiftAnd_1_sh8(i16 %x) {
; CHECK-LABEL: testShiftAnd_1_sh8:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov r12, r13
-; CHECK-NEXT: mov #128, r12
-; CHECK-NEXT: tst r13
-; CHECK-NEXT: jl .LBB10_2
-; CHECK-NEXT: ; %bb.1: ; %entry
-; CHECK-NEXT: clr r12
-; CHECK-NEXT: .LBB10_2: ; %entry
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: and #128, r12
; CHECK-NEXT: ret
entry:
%cmp = icmp slt i16 %x, 0
@@ -204,13 +197,11 @@ entry:
define i16 @testShiftAnd_1_sh9(i16 %x) {
; CHECK-LABEL: testShiftAnd_1_sh9:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov r12, r13
-; CHECK-NEXT: mov #64, r12
-; CHECK-NEXT: tst r13
-; CHECK-NEXT: jl .LBB11_2
-; CHECK-NEXT: ; %bb.1: ; %entry
-; CHECK-NEXT: clr r12
-; CHECK-NEXT: .LBB11_2: ; %entry
+; CHECK-NEXT: swpb r12
+; CHECK-NEXT: mov.b r12, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
+; CHECK-NEXT: and #64, r12
; CHECK-NEXT: ret
entry:
%cmp = icmp slt i16 %x, 0
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