[PATCH] D70157: Align branches within 32-Byte boundary

Tue Nov 12 18:55:42 PST 2019

skan created this revision.
skan added reviewers: xiangzhangllvm, LuoYuanke, pengfei, craig.topper.
Herald added subscribers: llvm-commits, cfe-commits, hiraditya.
Herald added projects: clang, LLVM.

Microcode update for Jump Conditional Code Erratum may cause performance
loss for some workloads:

https://www.intel.com/content/www/us/en/support/articles/000055650.html

Here is the patch to mitigate performance impact by aligning branches
within 32-byte boundary.  The impacted instructions are:

  a. Conditional jump.
  b. Fused conditional jump.
  c. Unconditional jump.
  d. Indirect jump.
  e. Ret.
  f. Call.

Add an option -mbranches-within-32B-boundaries to align branches within a
32-Byte boundary to reduce the potential performance loss of the microcode
update. The option is equivalent to the combination of three options:

-malign-branch-boundary=32
-malign-branch=fused-jcc-jmp
-malign-branch-prefix-size=5

and add -x86-branches-within-32B-boundaries for llvm-mc to enable
-x86-align-branch-boundary=32
-x86-align-branch=fused-jcc-jmp
-x86-align-branch-prefix-size=5

More fine options added for clang:

1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary.
2. -malign-branch=TYPE[-TYPE...] specifies types of branches to align.
3. -malign-branch-prefix-size=NUM limits the prefix size by NUM

per instruction.

The correponding options for llvm-mc are -x86-align-branch-boundary=NUM,
-x86-align-branch=TYPE[-TYPE...], -x86-align-branch-prefix-size=NUM.

A new MCFragment type, MCMachineDependentFragment, is added, which has
4 subtypes:

1. BranchPadding: The variable size frag to insert NOP before branch.
2. BranchPrefix: The variable size frag to insert segment prefixes to an instruction. The choice of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register.
3. FusedJccPadding: The variable size frag to insert NOP before fused conditional jump.
4. BranchSplit: The 0 size frag to separate the instruction which is fused with the following conditional jump from fused jcc

alignBranchesBegin and alignBranchesEnd are used to
insert MCMachineDependentFragment before instructions, relaxMachineDependent
grows or shrinks sizes of prefix and NOP to align the next branch frag:

1. First we try to add segment prefixes to instructions before a branch.
2. If there is no sufficient room to add segment prefixes, NOP will be

inserted before a branch.

NOP padding is disabled before tls_get_addr calls to keep TLS instruction
sequence unchanged.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70157

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/intel-align-branch.c
  clang/test/Driver/intel-align-branch.s
  llvm/include/llvm/MC/MCAsmBackend.h
  llvm/include/llvm/MC/MCAssembler.h
  llvm/include/llvm/MC/MCFragment.h
  llvm/lib/MC/MCAssembler.cpp
  llvm/lib/MC/MCFragment.cpp
  llvm/lib/MC/MCObjectStreamer.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86MacroFusion.cpp
  llvm/test/MC/X86/i386-align-branch-1a.s
  llvm/test/MC/X86/i386-align-branch-1b.s
  llvm/test/MC/X86/i386-align-branch-1c.s
  llvm/test/MC/X86/i386-align-branch-1d.s
  llvm/test/MC/X86/i386-align-branch-1e.s
  llvm/test/MC/X86/i386-align-branch-1f.s
  llvm/test/MC/X86/i386-align-branch-2a.s
  llvm/test/MC/X86/i386-align-branch-2b.s
  llvm/test/MC/X86/i386-align-branch-2c.s
  llvm/test/MC/X86/i386-align-branch-3a.s
  llvm/test/MC/X86/i386-align-branch-4a.s
  llvm/test/MC/X86/i386-align-branch-4b.s
  llvm/test/MC/X86/i386-align-branch-5a.s
  llvm/test/MC/X86/i386-align-branch-6a.s
  llvm/test/MC/X86/i386-align-branch-7a.s
  llvm/test/MC/X86/x86-64-align-branch-1a.s
  llvm/test/MC/X86/x86-64-align-branch-1b.s
  llvm/test/MC/X86/x86-64-align-branch-1c.s
  llvm/test/MC/X86/x86-64-align-branch-1d.s
  llvm/test/MC/X86/x86-64-align-branch-1e.s
  llvm/test/MC/X86/x86-64-align-branch-1f.s
  llvm/test/MC/X86/x86-64-align-branch-1g.s
  llvm/test/MC/X86/x86-64-align-branch-2a.s
  llvm/test/MC/X86/x86-64-align-branch-2b.s
  llvm/test/MC/X86/x86-64-align-branch-2c.s
  llvm/test/MC/X86/x86-64-align-branch-2d.s
  llvm/test/MC/X86/x86-64-align-branch-3a.s
  llvm/test/MC/X86/x86-64-align-branch-4a.s
  llvm/test/MC/X86/x86-64-align-branch-4b.s
  llvm/test/MC/X86/x86-64-align-branch-5a.s

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