[PATCH] D70085: [AMDGPU] NFC target dependent requiresUniformRegister refactored out
Alexander via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 12 06:25:12 PST 2019
alex-t updated this revision to Diff 228881.
alex-t added a comment.
Typo and formatting fixed.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70085/new/
https://reviews.llvm.org/D70085
Files:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.h
Index: llvm/lib/Target/AMDGPU/SIISelLowering.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -402,8 +402,9 @@
virtual const TargetRegisterClass *
getRegClassFor(MVT VT, bool isDivergent) const override;
- virtual bool requiresUniformRegister(MachineFunction &MF,
- const Value *V) const override;
+ virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
+ MachineFunction &MF, const Value *V) const override;
+ bool requiresUniformRegister(MachineFunction &MF, const Value *V) const;
Align getPrefLoopAlignment(MachineLoop *ML) const override;
void allocateHSAUserSGPRs(CCState &CCInfo,
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10970,6 +10970,12 @@
return RC;
}
+bool SITargetLowering::isDivergent(const LegacyDivergenceAnalysis *DA,
+ MachineFunction &MF, const Value *V) const {
+ return !requiresUniformRegister(MF, V) &&
+ TargetLoweringBase::isDivergent(DA, MF, V);
+}
+
static bool hasCFUser(const Value *V, SmallPtrSet<const Value *, 16> &Visited) {
if (!Visited.insert(V).second)
return false;
Index: llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -380,8 +380,7 @@
}
unsigned FunctionLoweringInfo::CreateRegs(const Value *V) {
- return CreateRegs(V->getType(), DA && !TLI->requiresUniformRegister(*MF, V) &&
- DA->isDivergent(V));
+ return CreateRegs(V->getType(), TLI->isDivergent(DA, *MF, V));
}
/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
Index: llvm/include/llvm/CodeGen/TargetLowering.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetLowering.h
+++ llvm/include/llvm/CodeGen/TargetLowering.h
@@ -28,6 +28,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/CodeGen/DAGCombine.h"
#include "llvm/CodeGen/ISDOpcodes.h"
@@ -703,12 +704,12 @@
return RC;
}
- /// Allows target to decide about the register class of the
- /// specific value that is live outside the defining block.
- /// Returns true if the value needs uniform register class.
- virtual bool requiresUniformRegister(MachineFunction &MF,
- const Value *) const {
- return false;
+ /// Allows target to decide about the divergence of the
+ /// specific value. Base class implementation returns true
+ /// if the Divergece Analysis exists and reports value as divergent.
+ virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
+ MachineFunction &MF, const Value *V) const {
+ return DA && DA->isDivergent(V);
}
/// Return the 'representative' register class for the specified value
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