[PATCH] D59710: [SLP] remove lower limit for forming reduction patterns

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added inline comments.


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Comment at: llvm/test/Transforms/SLPVectorizer/X86/hadd.ll:82-86
+; CHECK-NEXT:    [[RDX_SHUF1:%.*]] = shufflevector <2 x i64> [[A:%.*]], <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
+; CHECK-NEXT:    [[BIN_RDX2:%.*]] = add <2 x i64> [[RDX_SHUF1]], [[A]]
+; CHECK-NEXT:    [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[B:%.*]], <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
+; CHECK-NEXT:    [[BIN_RDX:%.*]] = add <2 x i64> [[RDX_SHUF]], [[B]]
+; CHECK-NEXT:    [[R01:%.*]] = shufflevector <2 x i64> [[BIN_RDX2]], <2 x i64> [[BIN_RDX]], <2 x i32> <i32 0, i32 2>
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This one is worse than it was before for SSE


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59710/new/

https://reviews.llvm.org/D59710