[llvm] 2ab1b8c - [WebAssembly] Handle multiple loads of splatted loads
Vlad Tsyrklevich via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 31 16:53:51 PDT 2019
I've reverted this commit, my previous revert of your other commit was in
error. This commit is the one that introduced the failing getVTList call.
On Thu, Oct 31, 2019 at 2:59 PM Thomas Lively via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
>
> Author: Thomas Lively
> Date: 2019-10-31T14:59:30-07:00
> New Revision: 2ab1b8c1ec452fb743f6cc5051e75a01039cabfe
>
> URL:
> https://github.com/llvm/llvm-project/commit/2ab1b8c1ec452fb743f6cc5051e75a01039cabfe
> DIFF:
> https://github.com/llvm/llvm-project/commit/2ab1b8c1ec452fb743f6cc5051e75a01039cabfe.diff
>
> LOG: [WebAssembly] Handle multiple loads of splatted loads
>
> Summary:
> Fixes an ISel failure when a splatted load is used more than once. The
> failure was due to the hacks we were doing in ISel lowering to
> preserve the original load as the operand of a LOAD_SPLAT node. The
> fix is to properly lower the splatted use of the load to a separate
> LOAD_SPLAT node.
>
> Reviewers: aheejin
>
> Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish,
> llvm-commits
>
> Tags: #llvm
>
> Differential Revision: https://reviews.llvm.org/D69640
>
> Added:
> llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
>
> Modified:
> llvm/lib/Target/WebAssembly/WebAssemblyISD.def
> llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
> llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
> llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
>
> Removed:
>
>
>
>
> ################################################################################
> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def
> b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def
> index 13f0476eb4a5..ba04fd4eb9dd 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def
> @@ -30,9 +30,9 @@ HANDLE_NODETYPE(SWIZZLE)
> HANDLE_NODETYPE(VEC_SHL)
> HANDLE_NODETYPE(VEC_SHR_S)
> HANDLE_NODETYPE(VEC_SHR_U)
> -HANDLE_NODETYPE(LOAD_SPLAT)
> HANDLE_NODETYPE(THROW)
> HANDLE_NODETYPE(MEMORY_COPY)
> HANDLE_NODETYPE(MEMORY_FILL)
>
> -// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
> +// Memory intrinsics
> +HANDLE_MEM_NODETYPE(LOAD_SPLAT)
>
> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
> b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
> index 2f698711a746..5cb796e389f2 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
> @@ -466,11 +466,14 @@ const char *
> WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
> switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
> case WebAssemblyISD::FIRST_NUMBER:
> + case WebAssemblyISD::FIRST_MEM_OPCODE:
> break;
> #define HANDLE_NODETYPE(NODE)
> \
> case WebAssemblyISD::NODE:
> \
> return "WebAssemblyISD::" #NODE;
> +#define HANDLE_MEM_NODETYPE(NODE) HANDLE_NODETYPE(NODE)
> #include "WebAssemblyISD.def"
> +#undef HANDLE_MEM_NODETYPE
> #undef HANDLE_NODETYPE
> }
> return nullptr;
> @@ -1432,7 +1435,11 @@ SDValue
> WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op,
> if (Subtarget->hasUnimplementedSIMD128() &&
> (SplattedLoad = dyn_cast<LoadSDNode>(SplatValue)) &&
> SplattedLoad->getMemoryVT() == VecT.getVectorElementType()) {
> - Result = DAG.getNode(WebAssemblyISD::LOAD_SPLAT, DL, VecT,
> SplatValue);
> + Result = DAG.getMemIntrinsicNode(
> + WebAssemblyISD::LOAD_SPLAT, DL, DAG.getVTList({VecT}),
> + {SplattedLoad->getChain(), SplattedLoad->getBasePtr(),
> + SplattedLoad->getOffset()},
> + SplattedLoad->getMemoryVT(), SplattedLoad->getMemOperand());
> } else {
> Result = DAG.getSplatBuildVector(VecT, DL, SplatValue);
> }
>
> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
> b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
> index 90936670c471..58e088a0ba50 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
> @@ -24,8 +24,16 @@ namespace WebAssemblyISD {
> enum NodeType : unsigned {
> FIRST_NUMBER = ISD::BUILTIN_OP_END,
> #define HANDLE_NODETYPE(NODE) NODE,
> +#define HANDLE_MEM_NODETYPE(NODE)
> #include "WebAssemblyISD.def"
> + FIRST_MEM_OPCODE = ISD::FIRST_TARGET_MEMORY_OPCODE,
> #undef HANDLE_NODETYPE
> +#undef HANDLE_MEM_NODETYPE
> +#define HANDLE_NODETYPE(NODE)
> +#define HANDLE_MEM_NODETYPE(NODE) NODE,
> +#include "WebAssemblyISD.def"
> +#undef HANDLE_NODETYPE
> +#undef HANDLE_MEM_NODETYPE
> };
>
> } // end namespace WebAssemblyISD
>
> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
> b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
> index fc5d73dac52e..751c565d37fd 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
> @@ -72,35 +72,30 @@ defm "" : SIMDLoadSplat<"v16x8", 195>;
> defm "" : SIMDLoadSplat<"v32x4", 196>;
> defm "" : SIMDLoadSplat<"v64x2", 197>;
>
> -def wasm_load_splat_t : SDTypeProfile<1, 1, []>;
> -def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT",
> wasm_load_splat_t>;
> -
> -foreach args = [["v16i8", "i32", "extloadi8"], ["v8i16", "i32",
> "extloadi16"],
> - ["v4i32", "i32", "load"], ["v2i64", "i64", "load"],
> - ["v4f32", "f32", "load"], ["v2f64", "f64", "load"]] in
> -def load_splat_#args[0] :
> - PatFrag<(ops node:$addr), (wasm_load_splat
> - (!cast<ValueType>(args[1]) (!cast<PatFrag>(args[2])
> node:$addr)))>;
> +def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>;
> +def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT",
> wasm_load_splat_t,
> + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
> +def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>;
>
> let Predicates = [HasUnimplementedSIMD128] in
> foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32",
> "v32x4"],
> ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64",
> "v64x2"]] in {
> def : LoadPatNoOffset<!cast<ValueType>(args[0]),
> - !cast<PatFrag>("load_splat_"#args[0]),
> + load_splat,
> !cast<NI>("LOAD_SPLAT_"#args[1])>;
> def : LoadPatImmOff<!cast<ValueType>(args[0]),
> - !cast<PatFrag>("load_splat_"#args[0]),
> + load_splat,
> regPlusImm,
> !cast<NI>("LOAD_SPLAT_"#args[1])>;
> def : LoadPatImmOff<!cast<ValueType>(args[0]),
> - !cast<PatFrag>("load_splat_"#args[0]),
> + load_splat,
> or_is_add,
> !cast<NI>("LOAD_SPLAT_"#args[1])>;
> def : LoadPatOffsetOnly<!cast<ValueType>(args[0]),
> - !cast<PatFrag>("load_splat_"#args[0]),
> + load_splat,
> !cast<NI>("LOAD_SPLAT_"#args[1])>;
> def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
> - !cast<PatFrag>("load_splat_"#args[0]),
> + load_splat,
> !cast<NI>("LOAD_SPLAT_"#args[1])>;
> }
>
>
> diff --git a/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
> b/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
> new file mode 100644
> index 000000000000..4e693c285a3f
> --- /dev/null
> +++ b/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
> @@ -0,0 +1,21 @@
> +; RUN: llc < %s -asm-verbose=false -verify-machineinstrs
> -disable-wasm-fallthrough-return-opt -wasm-keep-registers
> -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s
> +
> +; Regression test for an ISel failure when a splatted load had more
> +; than one use. The main tests for load_splat are in simd-offset.ll.
> +
> +target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
> +target triple = "wasm32-unknown-unknown"
> +
> +; CHECK-LABEL: load_splat:
> +; CHECK-NEXT: .functype load_splat (i32, i32) -> (i32)
> +; CHECK-NEXT: i32.load8_u $[[E:[0-9]+]]=, 0($0){{$}}
> +; CHECK-NEXT: v8x16.load_splat $push[[V:[0-9]+]]=, 0($0){{$}}
> +; CHECK-NEXT: v128.store 0($1), $pop[[V]]{{$}}
> +; CHECK-NEXT: return $[[E]]{{$}}
> +define i8 @load_splat(i8* %p, <16 x i8>* %out) {
> + %e = load i8, i8* %p
> + %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
> + %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32>
> zeroinitializer
> + store <16 x i8> %v2, <16 x i8>* %out
> + ret i8 %e
> +}
>
>
>
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