[PATCH] D69601: [Power9] Implement the vector extend sign instruction pattern match

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: nemanjai, jsji, hfinkel, PowerPC.
Herald added subscribers: wuzish, kbarton, hiraditya.
Herald added a project: LLVM.

Power9 has instructions to implement the semantics of SIGN_EXTEND_INREG for vector type. Mark it as legal and add the match pattern.


https://reviews.llvm.org/D69601

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/vector-extend-sign.ll

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