[PATCH] D69527: AMDGPU: Make VReg_1 only include 1 artificial register

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 28 13:32:01 PDT 2019


arsenm marked an inline comment as done.
arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:690
+def ARTIFICIAL_VGPR : SIReg <"invalid vgpr", 0> {
+  let isArtificial = 1;
+}
----------------
rampitec wrote:
> isAllocatable = 0 maybe?
That applies to register classes, not registers. The class also does need to be allocatable, since we need to create virtual registers with it


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