[PATCH] D69392: [ARM] MVE interleaving load and stores.

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, SjoerdMeijer, samparker, simon_tatham, ostannard.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

Now that we have the intrinsics, we can add VLD2/4 and VST2/4 lowering for MVE. This works the same way as Neon, recognising the load/shuffles combination and converting them into intrinsics in a pre-isel pass, which just calls getMaxSupportedInterleaveFactor, lowerInterleavedLoad and lowerInterleavedStore.

The main difference to Neon is that we do not have a VLD3 instruction.  Otherwise most of the code works very similarly, with just some minor differences in the form of the intrinsics to work around. VLD3 is disabled by making isLegalInterleavedAccessType return false for those cases.

We may need some other future adjustments, such as VLD4 take up half the available registers so should maybe cost more. This patch should get the basics in though.


https://reviews.llvm.org/D69392

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
  llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll

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