[PATCH] D69172: AMDGPU: Fix SMEM WAR hazard for gfx10 readlane

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

It is OK as a w/a, but real opcode should not appear that early.
@arsenm What is the reason to use MC opcode in the SIFrameLowering::emitEpilogue()?

  BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
          FuncInfo->getFrameOffsetReg())


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D69172/new/

https://reviews.llvm.org/D69172