[PATCH] D68982: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine

[Sanjay Patel via Phabricator via llvm-commits]

spatel added reviewers: efriedma, hfinkel, mehdi_amini, lebedev.ri, craig.topper.
spatel added a comment.

I understand the direction, and I think there's general agreement on it (adding some more potential reviewers based on the bug report and llvm-dev thread), but:

1. Add the tests in the patch description to a file in test/CodeGen/MSP430 as an NFC commit *before* applying this patch. Generate baseline test assertions for current asm using utils/update_llc_test_checks.py.
2. Split this patch up. In the 1st step, we can add the TLI hook and 1-2 usages of that hook that show a test diff for MSP430. Ideally, we can add small tests for each proposed usage of the TLI hook.



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9496
+    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+    if ( ShCt <= TLI.getShiftAmountThreshold(VT)) {
+      SDValue NotX = DAG.getNOT(DL, X, VT);
----------------
Formatting: extra space after parenthesis here.
Several places below have the same problem.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D68982/new/

https://reviews.llvm.org/D68982