[PATCH] D68982: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine

[Joan LLuch via Phabricator via llvm-commits]

joanlluch created this revision.
joanlluch added a reviewer: spatel.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

This is a proposal of a TLI hook to allow targets to relax the emission of shifts (Replaces D68957 <https://reviews.llvm.org/D68957>)

Contributes to a Fix for https://bugs.llvm.org/show_bug.cgi?id=43559

(please note that the diff is from Release/9.x)

Provides codegen improvements on current and future targets with no multiple shift instructions and cheap selects or branches.

For example for the MSP430, the following IR:

  ; Function Attrs: norecurse nounwind readnone
  define dso_local i16 @test2(i16 %a) local_unnamed_addr #0 {
  entry:
    %cmp = icmp slt i16 %a, 0
    %cond = select i1 %cmp, i16 2, i16 0
    ret i16 %cond
  }
  
  ; Function Attrs: norecurse nounwind readnone
  define dso_local i16 @test3(i16 %a) local_unnamed_addr #0 {
  entry:
    %cmp = icmp slt i16 %a, 0
    %cond = select i1 %cmp, i16 3, i16 0
    ret i16 %cond
  }
  
  ; Function Attrs: norecurse nounwind readnone
  define dso_local i16 @test4(i16 %a, i16 %b) local_unnamed_addr #0 {
  entry:
    %cmp = icmp sgt i16 %a, %b
    %cond = select i1 %cmp, i16 32, i16 0
    ret i16 %cond
  }

gets translated into this before the patch:

  	.globl	test2
  	.p2align	1
  	.type	test2, at function
  test2:
  	swpb	r12
  	mov.b	r12, r12
  	clrc
  	rrc	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	and	#2, r12
  	ret
  .Lfunc_end0:
  	.size	test2, .Lfunc_end0-test2
  
  	.globl	test3
  	.p2align	1
  	.type	test3, at function
  test3:
  	swpb	r12
  	sxt	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	rra	r12
  	and	#3, r12
  	ret
  .Lfunc_end1:
  	.size	test3, .Lfunc_end1-test3
  
  	.globl	test4
  	.p2align	1
  	.type	test4, at function
  test4:
  	mov	r12, r14
  	mov	#1, r12
  	cmp	r14, r13
  	jl	.LBB2_2
  	clr	r12
  .LBB2_2:
  	add	r12, r12
  	add	r12, r12
  	add	r12, r12
  	add	r12, r12
  	add	r12, r12
  	ret
  .Lfunc_end2:
  	.size	test4, .Lfunc_end2-test4

After applying the patch, the above code turns into:

  	.globl	test2
  	.p2align	1
  	.type	test2, at function
  test2:
  	mov	r12, r13
  	mov	#1, r12
  	tst	r13
  	jl	.LBB0_2
  	clr	r12
  .LBB0_2:
  	add	r12, r12
  	ret
  .Lfunc_end0:
  	.size	test2, .Lfunc_end0-test2
  
  	.globl	test3
  	.p2align	1
  	.type	test3, at function
  test3:
  	mov	r12, r13
  	mov	#3, r12
  	tst	r13
  	jl	.LBB1_2
  	clr	r12
  .LBB1_2:
  	ret
  .Lfunc_end1:
  	.size	test3, .Lfunc_end1-test3
  
  	.globl	test4
  	.p2align	1
  	.type	test4, at function
  test4:
  	mov	r12, r14
  	mov	#32, r12
  	cmp	r14, r13
  	jl	.LBB2_2
  	clr	r12
  .LBB2_2:
  	ret
  .Lfunc_end2:
  	.size	test4, .Lfunc_end2-test4




Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D68982

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
  llvm/lib/Target/MSP430/MSP430ISelLowering.h

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