[PATCH] D68828: [AMDGPU] Allow DPP combiner to work with REG_SEQUENCE

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 4 inline comments as done.
rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:459-462
+        if (OrigMI.getOperand(I).getReg() == DPPMovReg) {
+          FwdSubReg = OrigMI.getOperand(I + 1).getImm();
+          break;
+        }
----------------
arsenm wrote:
> I think this won't work in the case where the operand itself has a subregister. 
> Can you add a test with something like
> 
> %0:vreg_64 = REG_SEQUENCE %vreg_64.sub0, sub1, %vreg_64.1, sub0
> 
> I think you can use composeSubRegIndices here
It cannot directly happen because we are in SSA and def must be a result of mov_dpp, i.e. defining the whole register.
This can however happen if yet another reg_sequence is composed out of the first one. I have added checks and test.


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  https://reviews.llvm.org/D68828/new/

https://reviews.llvm.org/D68828