[PATCH] D68776: [mips] Fix loading "double" immediate into a GPR and FPR
Simon Atanasyan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 10 03:28:35 PDT 2019
atanasyan created this revision.
atanasyan added reviewers: Petar.Avramovic, petarj, mbrkusanin, mstojanovic.
Herald added subscribers: jrtc27, hiraditya, arichardson, sdardis.
Herald added a project: LLVM.
If a "double" (64-bit) value has zero low 32-bits, it's possible to load such value into a GP/FP registers as an instruction immediate. But now assembler loads only high 32-bits of the value.
For example, if a target register is GPR the `li.d $4, 1.0` instruction converts into the `lui $4, 16368` one. As a result, we get `0x3FF00000` in the register. While a correct representation of the `1.0` value is `0x3FF0000000000000`. The patch fixes that.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D68776
Files:
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/test/MC/Mips/macro-li.d.s
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