[PATCH] D67950: [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel

Tue Oct 8 21:14:36 PDT 2019

jsji accepted this revision as: jsji.
jsji added a comment.
This revision is now accepted and ready to land.

LGTM. It would be great if you can figure out why we still have difference in ARM tests, but it shouldn't block this.

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Comment at: llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll:48
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
-; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: bne .LBB0_1
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Why do we still have this difference? Shouldn't it be fixed as well?

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https://reviews.llvm.org/D67950