[PATCH] D67950: [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang updated this revision to Diff 223976.
steven.zhang marked an inline comment as done.
steven.zhang added a comment.

rebase the patch.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67950/new/

https://reviews.llvm.org/D67950

Files:
  llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
  llvm/test/TableGen/InvalidMCSchedClassDesc.td
  llvm/utils/TableGen/SubtargetEmitter.cpp


Index: llvm/utils/TableGen/SubtargetEmitter.cpp
===================================================================
--- llvm/utils/TableGen/SubtargetEmitter.cpp
+++ llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -1057,6 +1057,7 @@
         LLVM_DEBUG(dbgs() << ProcModel.ModelName
                           << " does not have resources for class " << SC.Name
                           << '\n');
+        SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
       }
     }
     // Sum resources across all operand writes.
Index: llvm/test/TableGen/InvalidMCSchedClassDesc.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/InvalidMCSchedClassDesc.td
@@ -0,0 +1,47 @@
+// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
+// Check if it is valid MCSchedClassDesc if didn't have the resources. 
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+
+let OutOperandList = (outs), InOperandList = (ins) in {
+  def Inst_A : Instruction; 
+  def Inst_B : Instruction; 
+}
+
+let CompleteModel = 0 in {
+  def SchedModel_A: SchedMachineModel;
+  def SchedModel_B: SchedMachineModel;
+  def SchedModel_C: SchedMachineModel;
+}
+
+// Inst_B didn't have the resoures, and it is invalid.
+// CHECK: SchedModel_ASchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             1
+// CHECK-NEXT: {DBGFIELD("Inst_B")             16383 
+let SchedModel = SchedModel_A in {
+  def Write_A : SchedWriteRes<[]>;
+  def : InstRW<[Write_A], (instrs Inst_A)>;
+}
+
+// Inst_A didn't have the resoures, and it is invalid.
+// CHECK: SchedModel_BSchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             16383 
+// CHECK-NEXT: {DBGFIELD("Inst_B")             1 
+let SchedModel = SchedModel_B in {
+  def Write_B: SchedWriteRes<[]>; 
+  def : InstRW<[Write_B], (instrs Inst_B)>;
+}
+
+// CHECK: SchedModel_CSchedClasses[] = {
+// CHECK: {DBGFIELD("Inst_A")             1
+// CHECK-NEXT: {DBGFIELD("Inst_B")             1
+let SchedModel = SchedModel_C in {
+  def Write_C: SchedWriteRes<[]>; 
+  def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>;
+}
+
+def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
+def ProcessorB: ProcessorModel<"ProcessorB", SchedModel_B, []>;
+def ProcessorC: ProcessorModel<"ProcessorC", SchedModel_C, []>;
Index: llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
===================================================================
--- llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
+++ llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
@@ -45,7 +45,6 @@
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
-; CHECK-REG-PRESSURE: ldr{{.*}}, [sp
 ; CHECK-REG-PRESSURE: bne .LBB0_1
 
 for.body:


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