[PATCH] D68635: [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10903
+
+static bool hasCFUser(const Value *V, SetVector<const Value *> &Visited) {
+  if (Visited.count(V))
----------------
Why SetVector and not SmallPtrSet as usual?


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10904
+static bool hasCFUser(const Value *V, SetVector<const Value *> &Visited) {
+  if (Visited.count(V))
+    return false;
----------------
You can do if (!Visited.insert(V)) return false;


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:3978
   // No VOP2 instructions support AGPRs.
-  if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
+  if (Src0.isReg() && RI.hasAGPRs(Register::isVirtualRegister(Src0.getReg())
+                                      ? MRI.getRegClass(Src0.getReg())
----------------
What's wrong with isAGPR() call?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68635/new/

https://reviews.llvm.org/D68635