[PATCH] D68635: [AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'

[Alexander via Phabricator via llvm-commits]

alex-t created this revision.
alex-t added a reviewer: rampitec.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm, qcolombet, MatzeB.
Herald added a project: LLVM.

After https://reviews.llvm.org/D59990 submit several issues were discovered.
Changes in common code were preserved but AMDGPU specific part was reverted to keep the backend working correctly.

Discovered issues were addressed in the following commits:

- https://reviews.llvm.org/D67662
- https://reviews.llvm.org/D67101
- https://reviews.llvm.org/D63953
- https://reviews.llvm.org/D63731

This change brings back AMDGPU specific changes.


https://reviews.llvm.org/D68635

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
  llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
  llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
  llvm/test/CodeGen/AMDGPU/commute-shifts.ll
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
  llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
  llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
  llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
  llvm/test/CodeGen/AMDGPU/fabs.ll
  llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
  llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
  llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
  llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
  llvm/test/CodeGen/AMDGPU/fneg.ll
  llvm/test/CodeGen/AMDGPU/fsub.ll
  llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
  llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
  llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
  llvm/test/CodeGen/AMDGPU/loop_break.ll
  llvm/test/CodeGen/AMDGPU/madak.ll
  llvm/test/CodeGen/AMDGPU/multilevel-break.ll
  llvm/test/CodeGen/AMDGPU/select-opt.ll
  llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
  llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
  llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
  llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
  llvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
  llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
  llvm/test/CodeGen/AMDGPU/valu-i1.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll

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