[PATCH] D68341: [AIX] TOC pseudo expansion for 64bit large + 64bit small + 32bit large modes

[Hubert Tong via Phabricator via llvm-commits]

hubert.reinterpretcast added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp:77
+    assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
+           "The first and the second operand of addis instruction"
+           " should be registers.");
----------------
Add "an" before "addis".


================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp:80
+
+    assert(dyn_cast<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) && 
+           "The third operand of addis instruction should be a symbol "
----------------
Do not use `dyn_cast` for its Boolean value. Use `isa`.


================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp:81
+    assert(dyn_cast<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) && 
+           "The third operand of addis instruction should be a symbol "
+	   "reference expression.");
----------------
Same comment regarding "an".


================
Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp:82
+           "The third operand of addis instruction should be a symbol "
+	   "reference expression.");
+
----------------
Add "if it is an expression at all" to the end of the sentence.


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Comment at: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:926
     // Into:      %xd = ADDIS8 %x2, sym at got@tlsgd at ha
-    assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
+    assert(IsPPC64 && "Not supported for 32-bit PowerPC");
     const MachineOperand &MO = MI->getOperand(2);
----------------
There is quite a bit of noise in this patch from these NFC changes. Please split them out.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3172
+let hasSideEffects = 0, isReMaterializable = 1 in {
+def ADDIStocHA: PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
+                      "#ADDIStocHA",
----------------
Why the whitespace change on this line? The surrounding `def`s have spaces around the colon.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68341/new/

https://reviews.llvm.org/D68341