[PATCH] D67046: [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook

[Sam Elliott via Phabricator via llvm-commits]

lenary added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/disjoint.ll:6
+; RUN:   -o /dev/null 2>&1 | FileCheck %s
+
+define i32 @test_disjoint(i32* %P, i32 %v) {
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Please can you write a few sentences explaining how this tests that these two SW's are disjoint?

I presume it's to do with the fact that the scheduler does not deem the `SW %1:gpr, %0:gpr, 8` to have to come after the first SW (it not being in the successors list).

Knowing how this tests the disjoint hook will help us understand how to update the test if the exact output ever changes.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67046/new/

https://reviews.llvm.org/D67046