[PATCH] D67046: [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 8 03:49:18 PDT 2019
luismarques updated this revision to Diff 223817.
luismarques added a comment.
Fix `RUN` lines and add `REQUIRES: asserts`.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67046/new/
https://reviews.llvm.org/D67046
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/test/CodeGen/RISCV/disjoint.ll
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