[PATCH] D68311: [X86] Rewrite to the vXi1 subvector insertion code to not rely on the value of bits that might be undef

[Benjamin Kramer via Phabricator via llvm-commits]

bkramer requested changes to this revision.
bkramer added a comment.
This revision now requires changes to proceed.

With the suggested changes this passes the test suite from https://github.com/google/jax with AVX512 enabled. I still don't see why the original code would be wrong though.



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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:5785
+                            DAG.getTargetConstant(LowShift, dl, MVT::i8));
+  Low = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec,
+                    DAG.getTargetConstant(LowShift, dl, MVT::i8));
----------------
s/Vec/Low/


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:5789
+  // Isolate the bits after the last inserted bit.
+  unsigned HighShift = NumElems - (IdxVal + SubVecNumElems);
+  SDValue High = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, Vec,
----------------
This should be something like `IdxVal + SubVecNumElems`


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:5792
+                            DAG.getTargetConstant(HighShift, dl, MVT::i8));
+  High = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, Vec,
+                    DAG.getTargetConstant(HighShift, dl, MVT::i8));
----------------
s/Vec/High/


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68311/new/

https://reviews.llvm.org/D68311