[llvm] r373413 - AMDGPU/GlobalISel: Legalize 1024-bit G_BUILD_VECTOR
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 1 18:02:18 PDT 2019
Author: arsenm
Date: Tue Oct 1 18:02:18 2019
New Revision: 373413
URL: http://llvm.org/viewvc/llvm-project?rev=373413&view=rev
Log:
AMDGPU/GlobalISel: Legalize 1024-bit G_BUILD_VECTOR
This will be needed to support AGPR operations.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=373413&r1=373412&r2=373413&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Tue Oct 1 18:02:18 2019
@@ -182,6 +182,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
const LLT V14S32 = LLT::vector(14, 32);
const LLT V15S32 = LLT::vector(15, 32);
const LLT V16S32 = LLT::vector(16, 32);
+ const LLT V32S32 = LLT::vector(32, 32);
const LLT V2S64 = LLT::vector(2, 64);
const LLT V3S64 = LLT::vector(3, 64);
@@ -190,12 +191,13 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
const LLT V6S64 = LLT::vector(6, 64);
const LLT V7S64 = LLT::vector(7, 64);
const LLT V8S64 = LLT::vector(8, 64);
+ const LLT V16S64 = LLT::vector(16, 64);
std::initializer_list<LLT> AllS32Vectors =
{V2S32, V3S32, V4S32, V5S32, V6S32, V7S32, V8S32,
- V9S32, V10S32, V11S32, V12S32, V13S32, V14S32, V15S32, V16S32};
+ V9S32, V10S32, V11S32, V12S32, V13S32, V14S32, V15S32, V16S32, V32S32};
std::initializer_list<LLT> AllS64Vectors =
- {V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64};
+ {V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64, V16S64};
const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
@@ -930,8 +932,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
auto &BuildVector = getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalForCartesianProduct(AllS32Vectors, {S32})
.legalForCartesianProduct(AllS64Vectors, {S64})
- .clampNumElements(0, V16S32, V16S32)
- .clampNumElements(0, V2S64, V8S64);
+ .clampNumElements(0, V16S32, V32S32)
+ .clampNumElements(0, V2S64, V16S64);
if (ST.hasScalarPackInsts())
BuildVector.legalFor({V2S16, S32});
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir?rev=373413&r1=373412&r2=373413&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir Tue Oct 1 18:02:18 2019
@@ -437,6 +437,81 @@ body: |
S_NOP 0, implicit %16
...
---
+name: legal_v32s32
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31
+ ; CHECK-LABEL: name: legal_v32s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
+ ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
+ ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr16
+ ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr17
+ ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr18
+ ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr19
+ ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr20
+ ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr21
+ ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr22
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr23
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
+ ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
+ ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
+ ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
+ ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
+ ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<32 x s32>)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = COPY $vgpr2
+ %3:_(s32) = COPY $vgpr3
+ %4:_(s32) = COPY $vgpr4
+ %5:_(s32) = COPY $vgpr5
+ %6:_(s32) = COPY $vgpr6
+ %7:_(s32) = COPY $vgpr7
+ %8:_(s32) = COPY $vgpr8
+ %9:_(s32) = COPY $vgpr9
+ %10:_(s32) = COPY $vgpr10
+ %11:_(s32) = COPY $vgpr11
+ %12:_(s32) = COPY $vgpr12
+ %13:_(s32) = COPY $vgpr13
+ %14:_(s32) = COPY $vgpr14
+ %15:_(s32) = COPY $vgpr15
+ %16:_(s32) = COPY $vgpr16
+ %17:_(s32) = COPY $vgpr17
+ %18:_(s32) = COPY $vgpr18
+ %19:_(s32) = COPY $vgpr19
+ %20:_(s32) = COPY $vgpr20
+ %21:_(s32) = COPY $vgpr21
+ %22:_(s32) = COPY $vgpr22
+ %23:_(s32) = COPY $vgpr23
+ %24:_(s32) = COPY $vgpr24
+ %25:_(s32) = COPY $vgpr25
+ %26:_(s32) = COPY $vgpr26
+ %27:_(s32) = COPY $vgpr27
+ %28:_(s32) = COPY $vgpr28
+ %29:_(s32) = COPY $vgpr29
+ %30:_(s32) = COPY $vgpr30
+ %31:_(s32) = COPY $vgpr31
+ %32:_(<32 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31
+ S_NOP 0, implicit %32
+...
+---
name: legal_v2s64
body: |
bb.0:
@@ -585,6 +660,50 @@ body: |
...
---
+name: legal_v16s64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11, $vgpr12_vgpr13, $vgpr14_vgpr15, $vgpr16_vgpr17, $vgpr18_vgpr19, $vgpr20_vgpr21, $vgpr22_vgpr23, $vgpr24_vgpr25, $vgpr26_vgpr27, $vgpr28_vgpr29, $vgpr30_vgpr31
+ ; CHECK-LABEL: name: legal_v16s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $vgpr6_vgpr7
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $vgpr8_vgpr9
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $vgpr10_vgpr11
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $vgpr12_vgpr13
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $vgpr14_vgpr15
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY $vgpr16_vgpr17
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s64) = COPY $vgpr18_vgpr19
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s64) = COPY $vgpr20_vgpr21
+ ; CHECK: [[COPY11:%[0-9]+]]:_(s64) = COPY $vgpr22_vgpr23
+ ; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY $vgpr24_vgpr25
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY $vgpr26_vgpr27
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s64) = COPY $vgpr28_vgpr29
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s64) = COPY $vgpr30_vgpr31
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64), [[COPY6]](s64), [[COPY7]](s64), [[COPY8]](s64), [[COPY9]](s64), [[COPY10]](s64), [[COPY11]](s64), [[COPY12]](s64), [[COPY13]](s64), [[COPY14]](s64), [[COPY15]](s64)
+ ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<16 x s64>)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = COPY $vgpr4_vgpr5
+ %3:_(s64) = COPY $vgpr6_vgpr7
+ %4:_(s64) = COPY $vgpr8_vgpr9
+ %5:_(s64) = COPY $vgpr10_vgpr11
+ %6:_(s64) = COPY $vgpr12_vgpr13
+ %7:_(s64) = COPY $vgpr14_vgpr15
+ %8:_(s64) = COPY $vgpr16_vgpr17
+ %9:_(s64) = COPY $vgpr18_vgpr19
+ %10:_(s64) = COPY $vgpr20_vgpr21
+ %11:_(s64) = COPY $vgpr22_vgpr23
+ %12:_(s64) = COPY $vgpr24_vgpr25
+ %13:_(s64) = COPY $vgpr26_vgpr27
+ %14:_(s64) = COPY $vgpr28_vgpr29
+ %15:_(s64) = COPY $vgpr30_vgpr31
+ %16:_(<16 x s64>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15
+ S_NOP 0, implicit %16
+...
+
+---
name: legal_v2s128
body: |
bb.0:
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir?rev=373413&r1=373412&r2=373413&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir Tue Oct 1 18:02:18 2019
@@ -550,53 +550,49 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[DEF]](<32 x s32>)
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
; CHECK: G_BR %bb.2
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>)
- ; CHECK: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32), [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32), [[UV64:%[0-9]+]]:_(s32), [[UV65:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV34]]
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV35]]
- ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV36]]
- ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV37]]
- ; CHECK: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV38]]
- ; CHECK: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV39]]
- ; CHECK: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV8]], [[UV40]]
- ; CHECK: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[UV41]]
- ; CHECK: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UV10]], [[UV42]]
- ; CHECK: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[UV11]], [[UV43]]
- ; CHECK: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[UV12]], [[UV44]]
- ; CHECK: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UV13]], [[UV45]]
- ; CHECK: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UV14]], [[UV46]]
- ; CHECK: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[UV47]]
- ; CHECK: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[UV16]], [[UV48]]
- ; CHECK: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UV17]], [[UV49]]
- ; CHECK: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UV18]], [[UV50]]
- ; CHECK: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[UV19]], [[UV51]]
- ; CHECK: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[UV20]], [[UV52]]
- ; CHECK: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[UV21]], [[UV53]]
- ; CHECK: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[UV22]], [[UV54]]
- ; CHECK: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[UV23]], [[UV55]]
- ; CHECK: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[UV24]], [[UV56]]
- ; CHECK: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UV25]], [[UV57]]
- ; CHECK: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UV26]], [[UV58]]
- ; CHECK: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[UV27]], [[UV59]]
- ; CHECK: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[UV28]], [[UV60]]
- ; CHECK: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[UV29]], [[UV61]]
- ; CHECK: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[UV30]], [[UV62]]
- ; CHECK: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UV31]], [[UV63]]
- ; CHECK: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[UV32]], [[UV64]]
- ; CHECK: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UV33]], [[UV65]]
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>)
+ ; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32), [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<32 x s32>)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV32]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV33]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV34]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV35]]
+ ; CHECK: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV36]]
+ ; CHECK: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV37]]
+ ; CHECK: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV38]]
+ ; CHECK: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV39]]
+ ; CHECK: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UV8]], [[UV40]]
+ ; CHECK: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[UV41]]
+ ; CHECK: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[UV10]], [[UV42]]
+ ; CHECK: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UV11]], [[UV43]]
+ ; CHECK: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UV12]], [[UV44]]
+ ; CHECK: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[UV13]], [[UV45]]
+ ; CHECK: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[UV14]], [[UV46]]
+ ; CHECK: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[UV47]]
+ ; CHECK: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UV16]], [[UV48]]
+ ; CHECK: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[UV17]], [[UV49]]
+ ; CHECK: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[UV18]], [[UV50]]
+ ; CHECK: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[UV19]], [[UV51]]
+ ; CHECK: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[UV20]], [[UV52]]
+ ; CHECK: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[UV21]], [[UV53]]
+ ; CHECK: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[UV22]], [[UV54]]
+ ; CHECK: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UV23]], [[UV55]]
+ ; CHECK: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UV24]], [[UV56]]
+ ; CHECK: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[UV25]], [[UV57]]
+ ; CHECK: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[UV26]], [[UV58]]
+ ; CHECK: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[UV27]], [[UV59]]
+ ; CHECK: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[UV28]], [[UV60]]
+ ; CHECK: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UV29]], [[UV61]]
+ ; CHECK: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[UV30]], [[UV62]]
+ ; CHECK: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UV31]], [[UV63]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32), [[ADD8]](s32), [[ADD9]](s32), [[ADD10]](s32), [[ADD11]](s32), [[ADD12]](s32), [[ADD13]](s32), [[ADD14]](s32), [[ADD15]](s32), [[ADD16]](s32), [[ADD17]](s32), [[ADD18]](s32), [[ADD19]](s32), [[ADD20]](s32), [[ADD21]](s32), [[ADD22]](s32), [[ADD23]](s32), [[ADD24]](s32), [[ADD25]](s32), [[ADD26]](s32), [[ADD27]](s32), [[ADD28]](s32), [[ADD29]](s32), [[ADD30]](s32), [[ADD31]](s32)
- ; CHECK: [[UV66:%[0-9]+]]:_(<16 x s32>), [[UV67:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:_(<16 x s32>) = G_PHI [[UV]](<16 x s32>), %bb.0, [[UV66]](<16 x s32>), %bb.1
- ; CHECK: [[PHI1:%[0-9]+]]:_(<16 x s32>) = G_PHI [[UV1]](<16 x s32>), %bb.0, [[UV67]](<16 x s32>), %bb.1
- ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[PHI]](<16 x s32>), [[PHI1]](<16 x s32>)
- ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[CONCAT_VECTORS]](<32 x s32>)
+ ; CHECK: [[PHI:%[0-9]+]]:_(<32 x s32>) = G_PHI [[DEF]](<32 x s32>), %bb.0, [[BUILD_VECTOR]](<32 x s32>), %bb.1
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]](<32 x s32>)
bb.0:
successors: %bb.1, %bb.2
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
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