[llvm] r373412 - AMDGPU/GlobalISel: Fix RegBankSelect for 1024-bit values
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 1 18:02:14 PDT 2019
Author: arsenm
Date: Tue Oct 1 18:02:14 2019
New Revision: 373412
URL: http://llvm.org/viewvc/llvm-project?rev=373412&view=rev
Log:
AMDGPU/GlobalISel: Fix RegBankSelect for 1024-bit values
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def?rev=373412&r1=373411&r2=373412&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def Tue Oct 1 18:02:14 2019
@@ -22,15 +22,17 @@ enum PartialMappingIdx {
PM_SGPR128 = 9,
PM_SGPR256 = 10,
PM_SGPR512 = 11,
- PM_VGPR1 = 12,
- PM_VGPR16 = 16,
- PM_VGPR32 = 17,
- PM_VGPR64 = 18,
- PM_VGPR128 = 19,
- PM_VGPR256 = 20,
- PM_VGPR512 = 21,
- PM_SGPR96 = 22,
- PM_VGPR96 = 23
+ PM_SGPR1024 = 12,
+ PM_VGPR1 = 13,
+ PM_VGPR16 = 17,
+ PM_VGPR32 = 18,
+ PM_VGPR64 = 19,
+ PM_VGPR128 = 20,
+ PM_VGPR256 = 21,
+ PM_VGPR512 = 22,
+ PM_VGPR1024 = 23,
+ PM_SGPR96 = 24,
+ PM_VGPR96 = 25
};
const RegisterBankInfo::PartialMapping PartMappings[] {
@@ -45,6 +47,7 @@ const RegisterBankInfo::PartialMapping P
{0, 128, SGPRRegBank},
{0, 256, SGPRRegBank},
{0, 512, SGPRRegBank},
+ {0, 1024, SGPRRegBank},
{0, 1, VGPRRegBank}, // VGPR begin
{0, 16, VGPRRegBank},
@@ -53,8 +56,9 @@ const RegisterBankInfo::PartialMapping P
{0, 128, VGPRRegBank},
{0, 256, VGPRRegBank},
{0, 512, VGPRRegBank},
+ {0, 1024, VGPRRegBank},
{0, 96, SGPRRegBank},
- {0, 96, VGPRRegBank},
+ {0, 96, VGPRRegBank}
};
const RegisterBankInfo::ValueMapping ValMappings[] {
@@ -65,30 +69,32 @@ const RegisterBankInfo::ValueMapping Val
{&PartMappings[1], 1},
// SGPRs
- {&PartMappings[2], 1},
+ {&PartMappings[2], 1}, // 1
{nullptr, 0}, // Illegal power of 2 sizes
{nullptr, 0},
{nullptr, 0},
- {&PartMappings[3], 1},
- {&PartMappings[4], 1},
- {&PartMappings[5], 1},
- {&PartMappings[6], 1},
- {&PartMappings[7], 1},
- {&PartMappings[8], 1},
+ {&PartMappings[3], 1}, // 16
+ {&PartMappings[4], 1}, // 32
+ {&PartMappings[5], 1}, // 64
+ {&PartMappings[6], 1}, // 128
+ {&PartMappings[7], 1}, // 256
+ {&PartMappings[8], 1}, // 512
+ {&PartMappings[9], 1}, // 1024
- // VGPRs
- {&PartMappings[9], 1},
+ // VGPRs
+ {&PartMappings[10], 1}, // 1
{nullptr, 0},
{nullptr, 0},
{nullptr, 0},
- {&PartMappings[10], 1},
- {&PartMappings[11], 1},
- {&PartMappings[12], 1},
- {&PartMappings[13], 1},
- {&PartMappings[14], 1},
- {&PartMappings[15], 1},
- {&PartMappings[16], 1},
- {&PartMappings[17], 1}
+ {&PartMappings[11], 1}, // 16
+ {&PartMappings[12], 1}, // 32
+ {&PartMappings[13], 1}, // 64
+ {&PartMappings[14], 1}, // 128
+ {&PartMappings[15], 1}, // 256
+ {&PartMappings[16], 1}, // 512
+ {&PartMappings[17], 1}, // 1024
+ {&PartMappings[18], 1},
+ {&PartMappings[19], 1}
};
const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
@@ -116,7 +122,7 @@ const RegisterBankInfo::ValueMapping Val
enum ValueMappingIdx {
SCCStartIdx = 0,
SGPRStartIdx = 2,
- VGPRStartIdx = 12
+ VGPRStartIdx = 13
};
const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir?rev=373412&r1=373411&r2=373412&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir Tue Oct 1 18:02:14 2019
@@ -29,3 +29,31 @@ body: |
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_EXTRACT %0, 0
...
+
+---
+name: extract_s32_0_s1024_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+ ; CHECK-LABEL: name: extract_s32_0_s1024_v
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+ ; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s1024), 0
+ %0:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+ %1:_(s32) = G_EXTRACT %0, 0
+...
+
+---
+name: extract_s32_0_s1024_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; CHECK-LABEL: name: extract_s32_0_s1024_s
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s1024), 0
+ %0:_(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
+ %1:_(s32) = G_EXTRACT %0, 0
+...
More information about the llvm-commits
mailing list