[PATCH] D68090: Fix doc for t inline asm constraints for ARM/Thumb

[Pablo Barrio via Phabricator via llvm-commits]

pbarrio created this revision.
Herald added a subscriber: kristof.beyls.
Herald added a project: LLVM.

The constraint goes up to regs d15 and q7, not d16 and q8.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D68090

Files:
  llvm/docs/LangRef.rst


Index: llvm/docs/LangRef.rst
===================================================================
--- llvm/docs/LangRef.rst
+++ llvm/docs/LangRef.rst
@@ -3863,10 +3863,10 @@
   invalid.
 - ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
   ``d0-d31``, or ``q0-q15``.
+- ``t``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
+  ``d0-d15``, or ``q0-q7``.
 - ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
   ``d0-d7``, or ``q0-q3``.
-- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
-  ``q0-q8``.
 
 ARM's Thumb1 mode:
 
@@ -3883,10 +3883,10 @@
 - ``h``: A high GPR register (``r0-r7``).
 - ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
   ``d0-d31``, or ``q0-q15``.
+- ``t``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
+  ``d0-d15``, or ``q0-q7``.
 - ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
   ``d0-d7``, or ``q0-q3``.
-- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
-  ``q0-q8``.
 
 
 Hexagon:


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