[PATCH] D67423: [RISCV] Rename FPRs and use Register arithmetic

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

This LGTM, thanks. Added a few nits. I think Sam's suggestion of adding a helper function or two to handle the register arithmetic is worth evaluating, but doesn't need to be done in this patch.



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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:32
+static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
+static_assert(RISCV::F31_F == RISCV::F0_F + 31, "Register list not consecutive");
+static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
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clang-format wants to wrap this


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:34
+static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
+static_assert(RISCV::F31_D == RISCV::F0_D + 31, "Register list not consecutive");
+
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clang-format wants to wrap this


Repository:
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  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423