[llvm] r372629 - [InstCombine] dropRedundantMaskingOfLeftShiftInput(): pat. a/b with mask (PR42563)
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 23 10:04:14 PDT 2019
Author: lebedevri
Date: Mon Sep 23 10:04:14 2019
New Revision: 372629
URL: http://llvm.org/viewvc/llvm-project?rev=372629&view=rev
Log:
[InstCombine] dropRedundantMaskingOfLeftShiftInput(): pat. a/b with mask (PR42563)
Summary:
And this is **finally** the interesting part of that fold!
If we have a pattern `(x & (~(-1 << maskNbits))) << shiftNbits`,
we already know (have a fold) that will drop the `& (~(-1 << maskNbits))`
mask iff `(maskNbits+shiftNbits) u>= bitwidth(x)`.
But that is actually ignorant, there's more general fold here:
In this pattern, `(maskNbits+shiftNbits)` actually correlates
with the number of low bits that will remain in the final value.
So even if `(maskNbits+shiftNbits) u< bitwidth(x)`, we can still
fold, we will just need to apply a **constant** mask afterwards:
```
Name: a, normal+mask
%onebit = shl i32 -1, C1
%mask = xor i32 %onebit, -1
%masked = and i32 %mask, %x
%r = shl i32 %masked, C2
=>
%n0 = shl i32 %x, C2
%n1 = add i32 C1, C2
%n2 = zext i32 %n1 to i64
%n3 = shl i64 -1, %n2
%n4 = xor i64 %n3, -1
%n5 = trunc i64 %n4 to i32
%r = and i32 %n0, %n5
```
https://rise4fun.com/Alive/F5R
Naturally, old `%masked` will have to be one-use.
Similar fold exists for patterns c,d,e, will post patch later.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, xbolva00
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67677
Modified:
llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll
llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=372629&r1=372628&r2=372629&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Mon Sep 23 10:04:14 2019
@@ -152,6 +152,7 @@ dropRedundantMaskingOfLeftShiftInput(Bin
m_Shr(m_Shl(m_AllOnes(), m_Value(MaskShAmt)), m_Deferred(MaskShAmt));
Value *X;
+ Constant *NewMask;
if (match(Masked, m_c_And(m_CombineOr(MaskA, MaskB), m_Value(X)))) {
// Can we simplify (MaskShAmt+ShiftShAmt) ?
auto *SumOfShAmts = dyn_cast_or_null<Constant>(
@@ -166,8 +167,27 @@ dropRedundantMaskingOfLeftShiftInput(Bin
// bitwidth, we'll need to also produce a mask to keep SumOfShAmts low bits.
// So, does *any* channel need a mask?
if (!match(SumOfShAmts, m_SpecificInt_ICMP(ICmpInst::Predicate::ICMP_UGE,
- APInt(BitWidth, BitWidth))))
- return nullptr; // FIXME.
+ APInt(BitWidth, BitWidth)))) {
+ // But for a mask we need to get rid of old masking instruction.
+ if (!Masked->hasOneUse())
+ return nullptr; // Else we can't perform the fold.
+ // We should produce compute the mask in wider type, and truncate later!
+ // Get type twice as wide element-wise (same number of elements!).
+ Type *ExtendedScalarTy = Type::getIntNTy(Ty->getContext(), 2 * BitWidth);
+ Type *ExtendedTy =
+ Ty->isVectorTy()
+ ? VectorType::get(ExtendedScalarTy, Ty->getVectorNumElements())
+ : ExtendedScalarTy;
+ auto *ExtendedSumOfShAmts =
+ ConstantExpr::getZExt(SumOfShAmts, ExtendedTy);
+ // And compute the mask as usual: ~(-1 << (SumOfShAmts))
+ auto *ExtendedAllOnes = ConstantExpr::getAllOnesValue(ExtendedTy);
+ auto *ExtendedInvertedMask =
+ ConstantExpr::getShl(ExtendedAllOnes, ExtendedSumOfShAmts);
+ auto *ExtendedMask = ConstantExpr::getNot(ExtendedInvertedMask);
+ NewMask = ConstantExpr::getTrunc(ExtendedMask, Ty);
+ } else
+ NewMask = nullptr; // No mask needed.
// All good, we can do this fold.
} else if (match(Masked, m_c_And(m_CombineOr(MaskC, MaskD), m_Value(X))) ||
match(Masked, m_Shr(m_Shl(m_Value(X), m_Value(MaskShAmt)),
@@ -185,12 +205,19 @@ dropRedundantMaskingOfLeftShiftInput(Bin
if (!match(ShAmtsDiff, m_NonNegative()))
return nullptr; // FIXME.
// All good, we can do this fold.
+ NewMask = nullptr; // No mask needed.
} else
return nullptr; // Don't know anything about this pattern.
// No 'NUW'/'NSW'!
// We no longer know that we won't shift-out non-0 bits.
- return BinaryOperator::Create(OuterShift->getOpcode(), X, ShiftShAmt);
+ auto *NewShift =
+ BinaryOperator::Create(OuterShift->getOpcode(), X, ShiftShAmt);
+ if (!NewMask)
+ return NewShift;
+
+ Builder.Insert(NewShift);
+ return BinaryOperator::Create(Instruction::And, NewShift, NewMask);
}
Instruction *InstCombiner::commonShiftTransforms(BinaryOperator &I) {
Modified: llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll?rev=372629&r1=372628&r2=372629&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll Mon Sep 23 10:04:14 2019
@@ -18,13 +18,13 @@ define i32 @t0_basic(i32 %x, i32 %nbits)
; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1
; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[T1]], -1
-; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]]
; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: call void @use32(i32 [[T4]])
-; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T3]], [[T4]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], [[T4]]
+; CHECK-NEXT: [[T5:%.*]] = and i32 [[TMP1]], 2147483647
; CHECK-NEXT: ret i32 [[T5]]
;
%t0 = add i32 %nbits, -1
@@ -49,13 +49,13 @@ define <8 x i32> @t1_vec_splat(<8 x i32>
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]]
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
-; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
+; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
%t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
@@ -76,13 +76,13 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>
; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]]
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
-; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
+; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], <i32 undef, i32 0, i32 1, i32 2147483647, i32 -1, i32 -1, i32 -1, i32 undef>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
%t0 = add <8 x i32> %nbits, <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>
Modified: llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll?rev=372629&r1=372628&r2=372629&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll Mon Sep 23 10:04:14 2019
@@ -18,13 +18,13 @@ define i32 @t0_basic(i32 %x, i32 %nbits)
; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1
; CHECK-NEXT: [[T1:%.*]] = shl i32 -1, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = xor i32 [[T1]], -1
-; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]]
; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
; CHECK-NEXT: call void @use32(i32 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: call void @use32(i32 [[T4]])
-; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T3]], [[T4]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], [[T4]]
+; CHECK-NEXT: [[T5:%.*]] = and i32 [[TMP1]], 2147483647
; CHECK-NEXT: ret i32 [[T5]]
;
%t0 = add i32 %nbits, -1
@@ -49,13 +49,13 @@ define <8 x i32> @t1_vec_splat(<8 x i32>
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = xor <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]]
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
-; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
+; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
%t0 = add <8 x i32> %nbits, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
@@ -76,13 +76,13 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i
; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>
; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = xor <8 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[T3:%.*]] = and <8 x i32> [[T2]], [[X:%.*]]
; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
-; CHECK-NEXT: [[T5:%.*]] = shl <8 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
+; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP1]], <i32 undef, i32 0, i32 1, i32 2147483647, i32 -1, i32 -1, i32 -1, i32 undef>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
%t0 = add <8 x i32> %nbits, <i32 -33, i32 -32, i32 -31, i32 -1, i32 0, i32 1, i32 31, i32 32>
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