[PATCH] D67850: Fix missed case of switching getConstant to getTargetConstant. Try 2.
Sterling Augustine via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 20 11:52:03 PDT 2019
saugustine updated this revision to Diff 221085.
saugustine marked 2 inline comments as done.
saugustine added a comment.
Addressing comments.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67850/new/
https://reviews.llvm.org/D67850
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/GlobalISel/isel-blendi-gettargetconstant.ll
Index: llvm/test/CodeGen/X86/GlobalISel/isel-blendi-gettargetconstant.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/GlobalISel/isel-blendi-gettargetconstant.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -mattr=sse4.2 | FileCheck %s
+
+define void @csrot_(float* %0) {
+; CHECK-LABEL: csrot_:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: xorps %xmm0, %xmm1
+; CHECK-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],mem[1,2,3]
+; CHECK-NEXT: movlps %xmm1, (%rax)
+; CHECK-NEXT: retq
+1:
+ %2 = load float, float* %0, align 4
+ %3 = fsub float -0.000000e+00, %2
+ %4 = insertelement <2 x float> <float undef, float -0.000000e+00>, float %3, i32 0
+ store <2 x float> %4, <2 x float>* undef, align 8
+ ret void
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -17608,7 +17608,7 @@
// operand form.
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1,
- DAG.getConstant(1, dl, MVT::i8));
+ DAG.getTargetConstant(1, dl, MVT::i8));
}
// Create this as a scalar to vector..
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
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