[PATCH] D67698: [RISCV] Remove RA from reserved register to use as callee saved register

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 added a comment.

In D67698#1675370 <https://reviews.llvm.org/D67698#1675370>, @lenary wrote:

> We discussed this in the RISC-V meeting on 19 Sep 2019.
>
> - Pros: GCC for RISC-V and LLVM for ARM and AArch64 seem to do the same. It can help in situations with particularly bad register pressure requirements.
> - Cons: It can make debugging a lot harder, though this seems not to be an issue in GDB for RISC-V.
>
>   I think we don't want to have yet another configuration flag to control this.
>
>   It would be good to see some performance comparison, but I realise you may not be able to release internal benchmarks, and we have no public benchmarking system for RISC-V.


I can't reveal the detail of the benchmark, but the most significant case improve about 1%. It might be reasonable to free RA for register allocation since most of the backend already do so.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67698/new/

https://reviews.llvm.org/D67698