[PATCH] D67698: [RISCV] Remove RA from reserved register to use as callee saved register

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

We discussed this in the RISC-V meeting on 19 Sep 2019.

- Pros: GCC for RISC-V and LLVM for ARM and AArch64 seem to do the same. It can help in situations with particularly bad register pressure requirements.
- Cons: It can make debugging a lot harder, though this seems not to be an issue in GDB for RISC-V.

I think we don't want to have yet another configuration flag to control this.

It would be good to see some performance comparison, but I realise you may not be able to release internal benchmarks, and we have no public benchmarking system for RISC-V.


Repository:
  rL LLVM

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