[PATCH] D67423: [RISCV] Rename FPRs and use Register arithmetic

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

This is looking good. I have just one question this time.



================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:31
+static_assert(RISCV::F31_F == RISCV::F0_F + 31, "Register list not consecutive");
+static_assert(RISCV::F18_D == RISCV::F3_D + 15, "Register list not consecutive");
+
----------------
Why does this static assert not cover all 31 64-bit FP regs?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423