[PATCH] D67423: [RISCV] Rename FPRs and use Register arithmetic

[Luís Marques via Phabricator via llvm-commits]

luismarques updated this revision to Diff 219958.
luismarques retitled this revision from "[RISCV] Consistently use Register arithmetic" to "[RISCV] Rename FPRs and use Register arithmetic".
luismarques added a comment.

- Changes the FPRs Register identifiers, to ensure sequential enumeration:
  - `F0_32`-`F31_32` -> `F0_F`-`F31_F`
  - `F0_64`-`F31_64` -> `F0_D`-`F31_D`
  - These were chosen instead of `Fxx`/`Dxx` to better match the ISA spec names, although both options were reasonable.
- Now makes straighforward use of FPR Register arithmetic.
- Adds static asserts regarding the register ordering.
- Updates the FPR register matching, since the tablegen matches now default to the 64-bit regs.
- Tightens some `RegNo` bounds checks that were too loose on master.
- Updates the title to reflect the changed scope of the patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td

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