[PATCH] D61961: [PowerPC] Cust lower fpext v2f32 to v2f64 from extract_subvector v4f32

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

Other than the minor nits that you can feel free to fix on the commit, LGTM.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9632
+  case ISD::EXTRACT_SUBVECTOR: {
+    assert((Op0.getNumOperands()==2 || isa<ConstantSDNode>(Op0->getOperand(1)))
+     && "Node should have 2 operands with second one being a constant!");
----------------
nemanjai wrote:
> Nit: spaces around the `==`.
Two issues:
- The nit about spaces around `==` was not addressed
- We don't want the `||` but an `&&` since we want both two operands and a constant second operand. Then the parens are no longer required either.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9935
+    if (Subtarget.isLittleEndian())
+      DWord = !DWord;
+
----------------
Sorry, I should have mentioned this before...
It would be clearer that you're simply flipping the bit if you wrote this as
`DWord ^= 0x1` or `DWord = DWord ^ 0x1`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61961/new/

https://reviews.llvm.org/D61961