[PATCH] D67444: [ARM] Add isVectorReduction MCInstrDesc flag

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs added a comment.

In D67444#1667873 <https://reviews.llvm.org/D67444#1667873>, @SjoerdMeijer wrote:

> At this point I am not sure if we should "pollute" the generic MC description with this property, mainly because the ARM backend will be the only user, and it looks like this could be simple target hook switching over the opcodes, like already done in the added unittest. Not pretty, but very simple and effective....
>  At the same time, there is enough prior art here, adding all sorts of things, so I am in two minds. But I think I would more lean towards a target hook, because it's not very generic/widely used.


I agree that this could be implemented solely in the backend. The problem I see, however, is what happens when adding new reduction instructions, as someone adding a new tablegen def won't know to add it to where these instructions are checked. Adding the flag to tablegen makes it easier to spot and add.


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https://reviews.llvm.org/D67444