[PATCH] D67186: [ARM] Masked loads and stores

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

LGTM, with a nit inline



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Comment at: llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp:494
 
+bool ARMTTIImpl::isLegalMaskedLoad(Type *DataTy) {
+  if (!EnableMaskedLoadStores || !ST->hasMVEIntegerOps())
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You pointed out to me that this is new, and more correct than before. ;-)
This is what I tried to fix in the D67005, which I will abandon, because this looks good to me.


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Comment at: llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp:502
+    unsigned VecWidth = DataTy->getPrimitiveSizeInBits();
+    if (VecWidth != 128)
+      return false;
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Better is to replace `128` with `TTI->getRegisterBitWidth(true)`


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  https://reviews.llvm.org/D67186/new/

https://reviews.llvm.org/D67186