[PATCH] D61884: [RISCV] Support stack offset exceed 32-bit for RV64

[Sam Elliott via Phabricator via llvm-commits]

lenary requested changes to this revision.
lenary added a comment.
This revision now requires changes to proceed.

In D61884#1667185 <https://reviews.llvm.org/D61884#1667185>, @shiva0217 wrote:

> In D61884#1666175 <https://reviews.llvm.org/D61884#1666175>, @lenary wrote:
>
> > Nice, this is looking a lot better.
> >
> > I chatted to @asb about this this morning, and he's not sure of the value of using `t1` (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use `a0-5` if it wishes, which can be compressed, unlike `t1`. Do you have a justification for explicitly choosing `t1`?
>
>
> To my understanding, the caller saved registers which are not parameter registers(a0-7) could be used as temp register for prologue and epilogue without any spill because the lifetime of these registers won't cross function call, and it would start after prologue and end before the epilogue. For the virtual register, if there are not enough scratch registers, the allocator will try to spill one.  So choosing t1 could avoid spill and GCC choose t1, too.  If the offset need to be rematlize, the constant after spilit might not fit in the C extension instructions in most cases.


I see your point that t0 is guaranteed not to be live over a function call boundary.

If parameter registers `a0-7` are not being used to pass arguments, then their lifetime will also not cross the function call and they are effectively no different from the temp registers, as far as their usage in the ABI is concerned.

In the case where there are unallocated (general purpose) registers, presumably choosing a virtual GPR will choose an unallocated one, and not spill. LLVM should know that if a0-7 is used for argument passing, then it cannot be used for a spill.

I think if we have to spill, we should let the compiler choose the register that is cheapest to spill. And if we don't have to spill, choosing in allocation order is more important as we have put the compressible registers earlier in the GPR allocation order.

Thus, if we have the ability to let LLVM choose for us, then we should.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61884/new/

https://reviews.llvm.org/D61884