[PATCH] D61884: [RISCV] Support stack offset exceed 32-bit for RV64

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 added a comment.

In D61884#1666175 <https://reviews.llvm.org/D61884#1666175>, @lenary wrote:

> Nice, this is looking a lot better.
>
> I chatted to @asb about this this morning, and he's not sure of the value of using `t1` (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use `a0-5` if it wishes, which can be compressed, unlike `t1`. Do you have a justification for explicitly choosing `t1`?


To my understanding, the caller saved registers which are not parameter registers(a0-7) could be used as temp register for prologue and epilogue without any spill because the lifetime of these registers won't cross function call, and it would start after prologue and end before the epilogue. For the virtual register, if there are not enough scratch registers, the allocator will try to spill one.  So choosing t1 could avoid spill and GCC choose t1, too.  If the offset need to be rematlize, the constant after spilit might not fit in the C extension instructions in most cases.


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