[PATCH] D66973: [RISCV] Switch to the Machine Scheduler

[James Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/callee-saved-gprs.ll:46
+; RV32I-NEXT:    sw a1, 28(sp)
+; RV32I-NEXT:    addi a2, a0, %lo(var)
 ;
----------------
lenary wrote:
> We seem to have gained a `lw; sw` pair here. Not entirely sure why. There are a few additions like this in this testcase.
I assume these were previously scheduled after the `addi` but have now been hoisted. Note that these check lines do not continue to the end of the function, these are truncated, and manually created rather than using update_llc_test_checks.py for this file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66973/new/

https://reviews.llvm.org/D66973