[PATCH] D66973: [RISCV] Switch to the Machine Scheduler

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In D66973#1664698 <https://reviews.llvm.org/D66973#1664698>, @lenary wrote:

> In D66973#1653084 <https://reviews.llvm.org/D66973#1653084>, @jrtc27 wrote:
>
> > `%hi` and `%lo` don't need to be adjacent to relax them; the ABI has been designed with this in mind (and bfd keeps to that) So long as the result of the `%hi` is always "consumed" by a relaxable `%lo`, things will work.
>
>
> Does this apply even if there is another relocation between `%hi` and `%lo`?


Yes, it really doesn't matter. So long as the data dependency is there in the assembly (which it will be, because that's what we generate) it makes no difference *where* the instructions are. The relaxations available are: 1. deleting `lui rd, %hi(x)` and changing the `addi rd, rs1, %lo(x)` to `addi rd, gp, %gprel(x)` (if within 2K of gp) or `addi rd, x0, %lo(x)` (if in first 2K of memory) 2. changing `lui rd, %hi(x)` to `c.lui rd, %hi(x)` (but a `R_RISCV_RVC_LUI`) if `rd` is a valid register and `%hi(x)` is a valid immediate for `c.lui`. None of these care about adjacency or order; they could even be split across object files.

Footnote: I only talk about `addi` here; any I-type or S-type instruction works in its place.


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