[llvm] r371428 - [mips] Fix decoding of microMIPS JALX instruction
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 9 10:28:46 PDT 2019
Author: atanasyan
Date: Mon Sep 9 10:28:45 2019
New Revision: 371428
URL: http://llvm.org/viewvc/llvm-project?rev=371428&view=rev
Log:
[mips] Fix decoding of microMIPS JALX instruction
microMIPS jump and link exchange instruction stores a target in a
26-bits field. Despite other microMIPS JAL instructions these bits
are target address shifted right 2 bits [1]. The patch fixes the
JALX instruction decoding and uses 2-bit shift.
[1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set
Differential Revision: https://reviews.llvm.org/D67320
Modified:
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=371428&r1=371427&r2=371428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon Sep 9 10:28:45 2019
@@ -267,6 +267,13 @@ static DecodeStatus DecodeJumpTargetMM(M
uint64_t Address,
const void *Decoder);
+// DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target,
+// which is shifted left by 2 bit.
+static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeMem(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -2290,6 +2297,15 @@ static DecodeStatus DecodeJumpTargetMM(M
Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success;
}
+
+static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
+ Inst.addOperand(MCOperand::createImm(JumpOffset));
+ return MCDisassembler::Success;
+}
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
unsigned Value,
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=371428&r1=371427&r2=371428&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Mon Sep 9 10:28:45 2019
@@ -955,17 +955,18 @@ let DecoderNamespace = "MicroMips" in {
EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Jump Instructions
- let DecoderMethod = "DecodeJumpTargetMM" in
+ let DecoderMethod = "DecodeJumpTargetMM" in {
def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
-
- let DecoderMethod = "DecodeJumpTargetMM" in {
def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,
ISA_MICROMIPS32_NOT_MIPS32R6;
+ }
+
+ let DecoderMethod = "DecodeJumpTargetXMM" in
def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- }
+
def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=371428&r1=371427&r2=371428&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Mon Sep 9 10:28:45 2019
@@ -137,6 +137,7 @@
0x00 0xd4 0x98 0x02 # CHECK: j 1328
0x00 0xf4 0x98 0x02 # CHECK: jal 1328
0xe6 0x03 0x3c 0x0f # CHECK: jalr $ra, $6
+0x10 0xf0 0x34 0x00 # CHECK: jalx 4194512
0x07 0x00 0x3c 0x0f # CHECK: jr $7
0xc9 0x94 0x9a 0x02 # CHECK: beq $9, $6, 1336
0x46 0x40 0x9a 0x02 # CHECK: bgez $6, 1336
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=371428&r1=371427&r2=371428&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Mon Sep 9 10:28:45 2019
@@ -137,6 +137,7 @@
0xd4 0x00 0x02 0x98 # CHECK: j 1328
0xf4 0x00 0x02 0x98 # CHECK: jal 1328
0x03 0xe6 0x0f 0x3c # CHECK: jalr $ra, $6
+0xf0 0x10 0x00 0x34 # CHECK: jalx 4194512
0x00 0x07 0x0f 0x3c # CHECK: jr $7
0x94 0xc9 0x02 0x9a # CHECK: beq $9, $6, 1336
0x40 0x46 0x02 0x9a # CHECK: bgez $6, 1336
More information about the llvm-commits
mailing list