[PATCH] D67259: [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.

Fri Sep 6 06:06:14 PDT 2019

spatel added inline comments.

================
Comment at: llvm/test/CodeGen/X86/min-legal-vector-width.ll:4
+; Make sure CPUs default to prefer-256-bit
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=skylake-avx512 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=cascadelake | FileCheck %s
----------------
I assume the negative attributes are here to mask non-512 codegen diffs and keep this file focused on the vector width issue, but would it be valuable to actually check that those diffs are as intended (ie, add different prefixes if it's not too distracting)?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67259/new/

https://reviews.llvm.org/D67259