[PATCH] D67259: [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, chandlerc, echristo.
Herald added subscribers: ychen, hiraditya.
Herald added a project: LLVM.

AVX512 instructions can cause a frequency drop on these CPUs. This
can negate the performance gains from using wider vectors. Enabling
prefer-vector-width=256 will prevent generation of zmm registers
unless explicit 512 bit operations are used in the original source
code.

I believe gcc and icc both do something similar to this by default.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67259

Files:
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/min-legal-vector-width.ll
  llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
  llvm/test/Transforms/SLPVectorizer/X86/sqrt.ll


Index: llvm/test/Transforms/SLPVectorizer/X86/sqrt.ll
===================================================================
--- llvm/test/Transforms/SLPVectorizer/X86/sqrt.ll
+++ llvm/test/Transforms/SLPVectorizer/X86/sqrt.ll
@@ -3,7 +3,7 @@
 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 
Index: llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
+++ llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt %s -loop-vectorize -instcombine -simplifycfg -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake-avx512 -S | FileCheck %s
+; RUN: opt %s -loop-vectorize -instcombine -simplifycfg -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake-avx512 -mattr=-prefer-256-bit -S | FileCheck %s
 
 @bytes = global [128 x i8] zeroinitializer, align 16
 
Index: llvm/test/CodeGen/X86/min-legal-vector-width.ll
===================================================================
--- llvm/test/CodeGen/X86/min-legal-vector-width.ll
+++ llvm/test/CodeGen/X86/min-legal-vector-width.ll
@@ -1,5 +1,13 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl,avx512bw,avx512dq,prefer-256-bit | FileCheck %s
+; Make sure CPUs default to prefer-256-bit
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=skylake-avx512 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=cascadelake | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=cooperlake | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=cannonlake | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=icelake-client | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=icelake-server | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-fast-variable-shuffle,-avx512vnni,-avx512vbmi -mcpu=tigerlake | FileCheck %s
 
 ; This file primarily contains tests for specific places in X86ISelLowering.cpp that needed be made aware of the legalizer not allowing 512-bit vectors due to prefer-256-bit even though AVX512 is enabled.
 
Index: llvm/lib/Target/X86/X86.td
===================================================================
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -597,6 +597,7 @@
 
   // Skylake-AVX512
   list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAVX512,
+                                                  FeaturePrefer256Bit,
                                                   FeatureCDI,
                                                   FeatureDQI,
                                                   FeatureBWI,
@@ -630,6 +631,7 @@
 
   // Cannonlake
   list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
+                                                  FeaturePrefer256Bit,
                                                   FeatureCDI,
                                                   FeatureDQI,
                                                   FeatureBWI,


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