[PATCH] D65961: AMDGPU/SILoadStoreOptimizer: Optimize scanning for mergeable instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:181
+
+        // If an address has only one use then there will be on other
+        // instructions with the same address, so we can't merge this one.
----------------
Typo s/on/no


================
Comment at: llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:1589
+bool SILoadStoreOptimizer::optimizeBlock(
+                       std::list<std::list<CombineInfo> > &MergeableInsts) {
+  bool Modified = false;
----------------
Why std::list, and a std::list of lists?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65961/new/

https://reviews.llvm.org/D65961