[llvm] r371056 - [MIPS GlobalISel] Select G_FENCE
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 5 04:20:33 PDT 2019
Author: petar.avramovic
Date: Thu Sep 5 04:20:32 2019
New Revision: 371056
URL: http://llvm.org/viewvc/llvm-project?rev=371056&view=rev
Log:
[MIPS GlobalISel] Select G_FENCE
G_FENCE comes form fence instruction. For MIPS fence is generated in
AtomicExpandPass when atomic instruction gets surrounded with fence
instruction when needed.
G_FENCE arguments don't have LLT, because of that there is no job for
legalizer and regbankselect. Instruction select G_FENCE for MIPS32.
Differential Revision: https://reviews.llvm.org/D67181
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp?rev=371056&r1=371055&r2=371056&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp Thu Sep 5 04:20:32 2019
@@ -752,6 +752,10 @@ bool MipsInstructionSelector::select(Mac
I.eraseFromParent();
return true;
}
+ case G_FENCE: {
+ MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
+ break;
+ }
default:
return false;
}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir?rev=371056&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir Thu Sep 5 04:20:32 2019
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @atomic_load_i32(i32* %ptr) { ret void }
+
+...
+---
+name: atomic_load_i32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: atomic_load_i32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load monotonic 4 from %ir.ptr)
+ ; MIPS32: SYNC 0
+ ; MIPS32: $v0 = COPY [[LW]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
+ G_FENCE 4, 1
+ $v0 = COPY %1(s32)
+ RetRA implicit $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir?rev=371056&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir Thu Sep 5 04:20:32 2019
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @atomic_load_i32(i32* %ptr) { ret void }
+
+...
+---
+name: atomic_load_i32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: atomic_load_i32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4 from %ir.ptr)
+ ; MIPS32: G_FENCE 4, 1
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
+ G_FENCE 4, 1
+ $v0 = COPY %1(s32)
+ RetRA implicit $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll?rev=371056&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll Thu Sep 5 04:20:32 2019
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i32 @atomic_load_i32(i32* %ptr) {
+; MIPS32-LABEL: atomic_load_i32:
+; MIPS32: # %bb.0:
+; MIPS32-NEXT: lw $2, 0($4)
+; MIPS32-NEXT: sync
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+ %val = load atomic i32, i32* %ptr acquire, align 4
+ ret i32 %val
+}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir?rev=371056&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir Thu Sep 5 04:20:32 2019
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @atomic_load_i32(i32* %ptr) { ret void }
+
+...
+---
+name: atomic_load_i32
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: atomic_load_i32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4 from %ir.ptr)
+ ; MIPS32: G_FENCE 4, 1
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
+ G_FENCE 4, 1
+ $v0 = COPY %1(s32)
+ RetRA implicit $v0
+
+...
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