[llvm] r371055 - [MIPS GlobalISel] Select llvm.trap intrinsic

[Petar Avramovic via llvm-commits]

Author: petar.avramovic
Date: Thu Sep  5 04:16:37 2019
New Revision: 371055

URL: http://llvm.org/viewvc/llvm-project?rev=371055&view=rev
Log:
[MIPS GlobalISel] Select llvm.trap intrinsic

Select G_INTRINSIC_W_SIDE_EFFECTS for Intrinsic::trap for MIPS32
via legalizeIntrinsic.

Differential Revision: https://reviews.llvm.org/D67180

Added:
    llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir
    llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=371055&r1=371054&r2=371055&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Thu Sep  5 04:16:37 2019
@@ -219,8 +219,16 @@ bool MipsLegalizerInfo::legalizeCustom(M
   return true;
 }
 
-bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
+bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
+                                          MachineRegisterInfo &MRI,
                                           MachineIRBuilder &MIRBuilder) const {
+  const MipsSubtarget &ST =
+      static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
+  const MipsInstrInfo &TII = *ST.getInstrInfo();
+  const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
+  const RegisterBankInfo &RBI = *ST.getRegBankInfo();
+  MIRBuilder.setInstr(MI);
+
   switch (MI.getIntrinsicID()) {
   case Intrinsic::memcpy:
   case Intrinsic::memset:
@@ -230,6 +238,11 @@ bool MipsLegalizerInfo::legalizeIntrinsi
       return false;
     MI.eraseFromParent();
     return true;
+  case Intrinsic::trap: {
+    MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
+    MI.eraseFromParent();
+    return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
+  }
   default:
     break;
   }

Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir?rev=371055&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir Thu Sep  5 04:16:37 2019
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  declare void @llvm.trap()
+  define void @f() { ret void }
+
+...
+---
+name:            f
+alignment:       2
+body:             |
+  bb.1 (%ir-block.0):
+    ; MIPS32-LABEL: name: f
+    ; MIPS32: TRAP
+    ; MIPS32: RetRA
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
+    RetRA
+
+...
+
+

Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll?rev=371055&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll Thu Sep  5 04:16:37 2019
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+  declare void @llvm.trap()
+
+  define void @f() {
+; MIPS32-LABEL: f:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    break
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+    call void @llvm.trap()
+    ret void
+  }