[llvm] r371007 - AMDGPU/GlobalISel: Fix placeholder value used for addrspacecast
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 4 19:20:29 PDT 2019
Author: arsenm
Date: Wed Sep 4 19:20:29 2019
New Revision: 371007
URL: http://llvm.org/viewvc/llvm-project?rev=371007&view=rev
Log:
AMDGPU/GlobalISel: Fix placeholder value used for addrspacecast
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=371007&r1=371006&r2=371007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Wed Sep 4 19:20:29 2019
@@ -878,8 +878,9 @@ Register AMDGPULegalizerInfo::getSegment
Register QueuePtr = MRI.createGenericVirtualRegister(
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
- // FIXME: Placeholder until we can track the input registers.
- MIRBuilder.buildConstant(QueuePtr, 0xdeadbeef);
+ const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+ if (!loadInputValue(QueuePtr, MIRBuilder, &MFI->getArgInfo().QueuePtr))
+ return Register();
// Offset into amd_queue_t for group_segment_aperture_base_hi /
// private_segment_aperture_base_hi.
@@ -990,6 +991,8 @@ bool AMDGPULegalizerInfo::legalizeAddrSp
MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
Register ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
+ if (!ApertureReg.isValid())
+ return false;
Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
@@ -1298,10 +1301,9 @@ Register AMDGPULegalizerInfo::getLiveInR
bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
const ArgDescriptor *Arg) const {
- if (!Arg->isRegister())
+ if (!Arg->isRegister() || !Arg->getRegister().isValid())
return false; // TODO: Handle these
- assert(Arg->getRegister() != 0);
assert(Arg->getRegister().isPhysical());
MachineRegisterInfo &MRI = *B.getMRI();
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir?rev=371007&r1=371006&r2=371007&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir Wed Sep 4 19:20:29 2019
@@ -5,6 +5,10 @@
---
name: test_addrspacecast_p0_to_p1
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
+
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -28,6 +32,10 @@ body: |
---
name: test_addrspacecast_p1_to_p0
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
+
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -51,6 +59,9 @@ body: |
---
name: test_addrspacecast_p0_to_p4
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -74,6 +85,9 @@ body: |
---
name: test_addrspacecast_p4_to_p0
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -97,6 +111,9 @@ body: |
---
name: test_addrspacecast_p0_to_p999
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -120,6 +137,9 @@ body: |
---
name: test_addrspacecast_p999_to_p0
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -143,22 +163,26 @@ body: |
---
name: test_addrspacecast_p5_to_p0
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0
; VI-LABEL: name: test_addrspacecast_p5_to_p0
- ; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
- ; VI: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 0
- ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559
- ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64)
+ ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
+ ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP %4, [[C]](s64)
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4)
- ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p5), [[C]]
- ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p5)
+ ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), %0(p5), %2
+ ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT %0(p5)
; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32)
- ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]]
+ ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], %3
+ ; VI: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; VI: [[C1:%[0-9]+]]:_(p5) = G_CONSTANT i32 0
+ ; VI: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+ ; VI: [[COPY2:%[0-9]+]]:_(p4) = COPY [[COPY]](p4)
; VI: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
; GFX9-LABEL: name: test_addrspacecast_p5_to_p0
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
@@ -183,6 +207,9 @@ body: |
---
name: test_addrspacecast_p0_to_p5
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -218,22 +245,27 @@ body: |
---
name: test_addrspacecast_p3_to_p0
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
+
body: |
bb.0:
liveins: $vgpr0
; VI-LABEL: name: test_addrspacecast_p3_to_p0
- ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
- ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559
- ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64)
+ ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
+ ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP %4, [[C]](s64)
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4)
- ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p3), [[C]]
- ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
+ ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), %0(p3), %2
+ ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT %0(p3)
; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32)
- ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]]
+ ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], %3
+ ; VI: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; VI: [[C1:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
+ ; VI: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+ ; VI: [[COPY2:%[0-9]+]]:_(p4) = COPY [[COPY]](p4)
; VI: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
; GFX9-LABEL: name: test_addrspacecast_p3_to_p0
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -258,6 +290,9 @@ body: |
---
name: test_addrspacecast_p0_to_p3
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1
@@ -293,6 +328,9 @@ body: |
---
name: test_addrspacecast_v2p0_to_v2p1
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
@@ -325,6 +363,9 @@ body: |
---
name: test_addrspacecast_v2p1_to_v2p0
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
@@ -357,6 +398,9 @@ body: |
---
name: test_addrspacecast_v2p0_to_v2p3
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
@@ -407,31 +451,35 @@ body: |
---
name: test_addrspacecast_v2p3_to_v2p0
+machineFunctionInfo:
+ argumentInfo:
+ queuePtr: { reg: '$sgpr4_sgpr5' }
body: |
bb.0:
liveins: $vgpr0_vgpr1
; VI-LABEL: name: test_addrspacecast_v2p3_to_v2p0
- ; VI: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
- ; VI: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
- ; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
- ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559
- ; VI: [[COPY1:%[0-9]+]]:_(p4) = COPY [[C2]](p4)
- ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
- ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY1]], [[C3]](s64)
+ ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
+ ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP %8, [[C]](s64)
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4)
- ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C]]
- ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3)
+ ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), %3(p3), %6
+ ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT %3(p3)
; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32)
- ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]]
- ; VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64)
+ ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], %7
+ ; VI: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
+ ; VI: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
+ ; VI: [[C1:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
+ ; VI: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+ ; VI: [[COPY2:%[0-9]+]]:_(p4) = COPY [[COPY]](p4)
+ ; VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY2]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4)
- ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[C]]
- ; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3)
+ ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C1]]
+ ; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3)
; VI: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT1]](s32), [[LOAD1]](s32)
- ; VI: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C1]]
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0)
+ ; VI: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C2]]
+ ; VI: [[COPY3:%[0-9]+]]:_(p4) = COPY [[COPY]](p4)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT1]](p0), [[SELECT]](p0)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>)
; GFX9-LABEL: name: test_addrspacecast_v2p3_to_v2p0
; GFX9: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
More information about the llvm-commits
mailing list