[PATCH] D67131: [globalisel] Support trivial COPY in GISelKnownBits

[Daniel Sanders via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL370955: [globalisel] Support trivial COPY in GISelKnownBits (authored by dsanders, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D67131?vs=218554&id=218765#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67131/new/

https://reviews.llvm.org/D67131

Files:
  llvm/trunk/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
  llvm/trunk/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp


Index: llvm/trunk/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
===================================================================
--- llvm/trunk/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+++ llvm/trunk/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
@@ -19,11 +19,17 @@
   unsigned CopyReg = Copies[Copies.size() - 1];
   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
+  unsigned DstReg = FinalCopy->getOperand(1).getReg();
   GISelKnownBits Info(*MF);
   KnownBits Res = Info.getKnownBits(SrcReg);
   EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
   EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
+
+  KnownBits Res2 = Info.getKnownBits(DstReg);
+  EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
+  EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
 }
+
 TEST_F(GISelMITest, TestKnownBitsPtrToIntViceVersa) {
   StringRef MIRString = "  %3:_(s16) = G_CONSTANT i16 256\n"
                         "  %4:_(p0) = G_INTTOPTR %3\n"
Index: llvm/trunk/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ llvm/trunk/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -112,6 +112,19 @@
   default:
     TL.computeKnownBitsForTargetInstr(R, Known, DemandedElts, MRI, Depth);
     break;
+  case TargetOpcode::COPY: {
+    MachineOperand Dst = MI.getOperand(0);
+    MachineOperand Src = MI.getOperand(1);
+    // Look through trivial copies.
+    // We can't use NoSubRegister by name as it's defined by each target but
+    // it's always defined to be 0 by tablegen.
+    if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() &&
+        Src.getSubReg() == 0 /*NoSubRegister*/) {
+      // Don't increment Depth for this one since we didn't do any work.
+      computeKnownBitsImpl(Src.getReg(), Known, DemandedElts, Depth);
+    }
+    break;
+  }
   case TargetOpcode::G_CONSTANT: {
     auto CstVal = getConstantVRegVal(R, MRI);
     Known.One = *CstVal;


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