[PATCH] D67131: [globalisel] Support trivial COPY in GISelKnownBits
Daniel Sanders via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 3 15:32:21 PDT 2019
dsanders created this revision.
dsanders added a reviewer: aditya_nandakumar.
Herald added subscribers: Petar.Avramovic, volkan, hiraditya, rovka.
Herald added a project: LLVM.
Allow GISelKnownBits to look through the trivial case of TargetOpcode::COPY
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D67131
Files:
llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
Index: llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
===================================================================
--- llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+++ llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
@@ -19,11 +19,17 @@
unsigned CopyReg = Copies[Copies.size() - 1];
MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
unsigned SrcReg = FinalCopy->getOperand(1).getReg();
+ unsigned DstReg = FinalCopy->getOperand(1).getReg();
GISelKnownBits Info(*MF);
KnownBits Res = Info.getKnownBits(SrcReg);
EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
+
+ KnownBits Res2 = Info.getKnownBits(DstReg);
+ EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
+ EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
}
+
TEST_F(GISelMITest, TestKnownBitsPtrToIntViceVersa) {
StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n"
" %4:_(p0) = G_INTTOPTR %3\n"
Index: llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -112,6 +112,19 @@
default:
TL.computeKnownBitsForTargetInstr(R, Known, DemandedElts, MRI, Depth);
break;
+ case TargetOpcode::COPY: {
+ MachineOperand Dst = MI.getOperand(0);
+ MachineOperand Src = MI.getOperand(1);
+ // Look through trivial copies.
+ // We can't use NoSubRegister by name as it's defined by each target but
+ // it's always defined to be 0 by tablegen.
+ if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() &&
+ Src.getSubReg() == 0 /*NoSubRegister*/) {
+ // Don't increment Depth for this one since we didn't do any work.
+ computeKnownBitsImpl(Src.getReg(), Known, DemandedElts, Depth);
+ }
+ break;
+ }
case TargetOpcode::G_CONSTANT: {
auto CstVal = getConstantVRegVal(R, MRI);
Known.One = *CstVal;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D67131.218554.patch
Type: text/x-patch
Size: 2046 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190903/4ddc83ac/attachment.bin>
More information about the llvm-commits
mailing list